Semiconductor device for transmitting electrical signals between two circuits

• US 9,922,926 B2
• Filed: 03/04/2015
• Issued: 03/20/2018
• Est. Priority Date: 03/13/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Nakashiba, Yasutaka
• Primary Examiner(s): Kraig, William F
• Assistant Examiner(s): Malek, Maliheh
• Application Number:
  US14/638,287
• Publication Number:
  US 20150179572A1
• Time in Patent Office: 1,112 Days
• Field of Search: 257531, 257E21022, 438171, 438190, 438210, 438238, 438329, 438381, 3405721, 3405722, 3405724
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12041 LED

Abstract

A semiconductor device sends and receives electrical signals. The semiconductor device includes a first substrate provided with a first circuit region containing a first circuit; a multi-level interconnect structure provided on the first substrate; a first inductor provided in the multi-level interconnect structure so as to include the first circuit region; and a second inductor provided in the multi-level interconnect structure so as to include the first circuit region, wherein one of the first inductor and the second inductor is connected to the first circuit and the other of the first inductor and the second inductor is connected to a second circuit.

Claims

1. A semiconductor device, comprising:

a substrate provided with a circuit region including at least one transistor;

a multi-level interconnect structure provided over the substrate, the multi-level interconnect structure formed by alternately stacking insulation layers and interconnect layers, all circuits formed by the multi-level interconnect structure occupying an area over the substrate when seen in a planar view; and

a first inductor provided at a periphery of a first layer of the multi-level interconnect structure so as to enclose an entirety of the circuit region in the planar view.

5. The semiconductor device according to claim 1, wherein an entirety of the multi-level interconnect structure is located within a space surrounded by the first inductor and the second inductor.

6. The semiconductor device according to claim 5, wherein the first inductor occupies an outermost perimeter of the first layer in the planar view, and surrounds an entirety of the multi-level interconnect structure.

7. The semiconductor device according to claim 6, further comprising:

a plurality of external connection terminals; and

a second inductor located within a second layer of the multi-level interconnect structure above the first inductor and extending along a perimeter of the multi-level interconnect structure in the planar view such that the second inductor overlaps the first inductor,

wherein the entirety of the region over the substrate when seen in a planar view and an entirety of the plurality of external connection terminals are located within an area enclosed by the second inductor.

8. The semiconductor device according to claim 7, wherein a spacing between the first inductor and second inductor is smaller than a diameter of the first inductor and a diameter of the second inductor.

15. The semiconductor device according to claim 1, wherein the first inductor occupies a perimeter of the substrate in the planar view, and surrounds an entirety of the multi-level interconnect structure.

2. A semiconductor device, comprising:

a substrate provided with a circuit region;

a multi-level interconnect structure provided over the substrate, the multi-level interconnect structure formed by alternately stacking insulation layers and interconnect layers, all circuits formed by the multi-level interconnect structure occupying an area over the substrate when seen in a planar view;

a first inductor provided at a periphery of a first layer of the multi-level interconnect structure so as to enclose an entirety of the circuit region in the planar view;

a plurality of external connection terminals; and

a second inductor in a second layer of the multi-level interconnect structure different from the first layer occupied by the first inductor, the second inductor provided at a periphery of the second layer and overlapping the first inductor in the first layer,

wherein all of said external connection terminals are located within a region enclosed by the second inductor.

3. The semiconductor device according to claim 2, wherein the external connection terminal is a pad provided over the multi-level interconnect structure.

4. The semiconductor device according to claim 3, wherein the first inductor is provided in the multi-level interconnect structure so as to surround all transistors provided over the region of the substrate in the planar view.

9. A semiconductor device, comprising:

a substrate provided with a circuit region;

a multi-level interconnect structure provided over the substrate, the multi-level interconnect structure formed by alternately stacking insulation layers and interconnect layers, all circuits formed by the multi-level interconnect structure occupying an area over the substrate when seen in a planar view;

a first inductor provided at a periphery of a first layer of the multi-level interconnect structure so as to enclose an entirety of the circuit region in the planar view;

a second inductor located within a second layer of the multi-level interconnect structure above the first layer of the first inductor, and extending along a perimeter of the multi-level interconnect structure in the planar view such that the second inductor overlaps the first inductor.

10. The semiconductor device according to claim 9, further comprising:

a transmit driver, located within a region surrounded by the second inductor and in connection with a first end of the second inductor.

11. The semiconductor device according to claim 10, further comprising:

a plurality of external connection terminals,

an entirety of the plurality of external connection terminals located within the region enclosed by the second inductor.

12. The semiconductor device according to claim 10, wherein a spacing between the first inductor and second inductor is smaller than a diameter of the first inductor and a diameter of the second inductor.

13. The semiconductor device according to claim 11, wherein a spacing between the first inductor and second inductor is smaller than a diameter of the first inductor and a diameter of the second inductor.

14. The semiconductor device according to claim 9, wherein the first inductor is located in a lowermost layer of the multi-level interconnect structure and the second inductor is located in an uppermost interconnect layer of the multi-level interconnect structure.