Distributed pulse width modulation control

• US 9,928,771 B2
• Filed: 01/25/2016
• Issued: 03/27/2018
• Est. Priority Date: 12/24/2015
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: X-Celeprint Limited
• Inventors: Cok, Ronald S.
• Primary Examiner(s): Haley, Joseph
• Assistant Examiner(s): FRANK, EMILY J
• Application Number:
  US15/005,869
• Publication Number:
  US 20170186356A1
• Time in Patent Office: 792 Days
• Field of Search: None
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element

Abstract

A distributed pulse-width modulation system includes an array of pulse-width modulation elements, each element including a digital memory for storing a multi-bit digital value and a drive circuit that drives an output device in response to the multi-bit digital value stored in the digital memory. A system controller includes a memory for storing a multi-bit digital value for each element and a communication circuit for communicating each multi-bit digital value to each corresponding pulse-width modulation element.

Claims

1. A distributed pulse-width modulation system, comprising:

an array of pulse-width modulation elements, each element comprising;

a digital memory for storing a multi-bit digital value, and

a drive circuit that drives an output device in response to the multi-bit digital value stored in the digital memory; and

a system controller comprising;

a memory for storing a multi-bit digital value for each element, and

a communication circuit for communicating each multi-bit digital value to each corresponding pulse-width modulation element,

wherein the system controller comprises a timing circuit for providing timing signals to each element, wherein the timing signals control the rate at which the output device is driven in response to the multi-bit digital value stored in the digital memory,

wherein the system controller comprises a memory for storing a full-bit digital value for each element, wherein the full-bit digital value comprises a plurality of multi-bit digital values, and the communication circuit communicates each multi-bit digital value of the full-bit digital value to each corresponding element sequentially,

wherein the timing circuit, in response to the system controller, provides a timing signal with a first period for a first multi-bit digital value and provides a timing signal with a second period different from the first period for a second multi-bit digital value, and

wherein the first multi-bit digital value represents the lower bits of the full-bit digital value and the second multi-bit digital value represents the upper bits of the full-bit digital value and the first and second periods are related by the relative value of the lower bits and the upper bits in the full-bit digital value.

2. The system of claim 1, wherein the elements each comprise a counter that is responsive to the timing signal and the output device is responsive to the counter.

3. The system of claim 2, wherein the counter is a first counter and the system comprises:

a second counter responsive to the timing signal; and

a control circuit that alternates the signals from the first counter and the second counter, wherein the output device is responsive to the alternating signal.

4. The system of claim 1, wherein the system is a display system, the elements are pixel elements, the multi-bit digital value is a pixel value specifying light output, and the output device outputs light.

5. The system of claim 1, wherein the elements form an array of elements arranged in rows and columns.

6. The system of claim 5, wherein the system controller is an active-matrix controller for the array of elements.

7. The system of claim 1, wherein the drive circuit, in response to the pulse-width modulation element, sequentially provides a voltage or a current corresponding to the value of each bit of the multi-bit digital value.

8. The system of claim 7, wherein the drive circuit, in response to the pulse-width modulation element, supplies a constant current or voltage to the output device for a time period corresponding to the value of each bit of the multi-bit digital value.

9. The system of claim 8, wherein the system controller comprises a timing circuit for providing timing signals to each element, wherein the time period is formed with a counter controlled by the timing signal.

10. The system of claim 1, wherein the output device is a light-emitting diode.

11. The system of claim 1, wherein the display system comprises a plurality of light-emitting diodes and each output device is a light-emitting diode of the plurality of light-emitting diodes.

12. A method of controlling a distributed pulse-width modulation system according to claim 1, comprising:

providing an array of full-bit digital values, each full-bit digital value comprising a first multi-bit digital value and a second multi-bit digital value;

loading each element of the array of elements with the first multi-bit digital value of the array of full-bit digital values;

providing a first timing signal to each element;

combining the first timing signal and the first multi-bit digital value to provide a control signal in each element, the control signal responsive to the value of the first multi-bit digital value; and

driving the output device of each element in response to the control signal;

loading each element of the array of elements with the second multi-bit digital value of the array of full-bit digital values;

providing a second timing signal to each element;

combining the second timing signal and the second multi-bit digital value to provide a control signal in each element, the control signal responsive to the value of the second multi-bit digital value; and

driving the output device of each element in response to the control signal.

13. The method of claim 12, wherein the rate of the first timing signal and the rate of the second timing signal are related by the relative value of the lower bits and the upper bits in the full-bit digital value.

14. The method of claim 12, wherein the timing signal for different elements are relatively out of phase.

15. A distributed pulse-width modulation system, comprising:

an array of pulse-width modulation elements, each element comprising;

a digital memory for storing a multi-bit digital value,

a drive circuit that drives an output device in response to the multi-bit digital value stored in the digital memory,

a first counter and a second counter, and

a control circuit that alternates signals from the first counter and the second counter, wherein the output device is responsive to the alternating signals;

a system controller comprising;

a memory for storing a multi-bit digital value for each element, and

a communication circuit for communicating each multi-bit digital value to each corresponding pulse-width modulation element; and

a timing circuit for providing timing signals to each element, wherein the timing signals control the rate at which the output device is driven in response to the multi-bit digital value stored in the digital memory,

wherein the first and second counters in each element are responsive to the timing signal.