Apparatuses and methods for comparing data patterns in memory

• US 9,934,856 B2
• Filed: 03/25/2015
• Issued: 04/03/2018
• Est. Priority Date: 03/31/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A.
• Primary Examiner(s): Hur, J. H.
• Application Number:
  US14/667,868
• Publication Number:
  US 20150279466A1
• Time in Patent Office: 1,105 Days
• Field of Search: None
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 15/043 using capacitive charge storage elements
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

Apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array to a target data pattern. The method can include determining whether a data pattern of the number of data patterns matches the target data pattern without transferring data from the memory array via an input/output (I/O) line.

Claims

1. A method for comparing data patterns, comprising:

comparing in sensing circuitry a number of data patterns stored in a memory array to a target data pattern by;

storing a first data value of a first data unit of the target data pattern in a compute component;

logically ORing a data value of a first data unit of a first of the number of data patterns with the first data value stored in the compute component and store a result of the logical OR operation in the compute component;

wherein the first data unit of the stored data pattern and the first data unit of the target data pattern have a same data unit position;

comparing of a second data unit of the target data pattern to a second data unit of the stored data pattern by;

inverting of the result of the logical OR operation stored in the compute component; and

performing of a logical AND of the inverted result of the logical OR operation with a data value of the second data unit of the stored first data pattern and storing of a result of the logical AND operation in the compute component;

the second data unit of the target data pattern having a second data value, and wherein the second data unit of the stored data pattern and the second data unit of the target data pattern have a same data unit position; and

determining whether a data pattern of the number of data patterns matches the target data pattern.

2. The method of claim 1, wherein whether the data pattern of the number of data patterns matches the target data pattern is determined without transferring data from the memory array via an input/output (I/O) line.

3. The method of claim 1, wherein comparing the number of data patterns stored in the memory array to the target data pattern comprises performing a particular number of operations using the sensing circuitry, wherein the particular number of operations is based on a number of data units of the target data pattern.

4. The method of claim 1, wherein an amount of time to compare the number of data patterns stored in the memory array to the target data pattern is independent of the number of data patterns.

5. The method of claim 1, wherein:

the number of data patterns each comprise a plurality of data units, and

each of the plurality of data units of a particular one of the number of data patterns is stored in a different memory cell coupled to a same sense line of the array.

6. The method of claim 5, wherein a first data unit of the plurality of data units of each of the number of data patterns is stored in a respective memory cell coupled to a first access line of the array and a second data unit of each of the number of data patterns is stored in a respective memory cell coupled to a second access line.

7. The method of claim 1, wherein comparing the number of data patterns comprises comparing a data value of each data unit of the data patterns stored in memory cells coupled to an access line to a first data value of the target data pattern.

8. The method of claim 7, wherein the first data value comprises a “

0”

.

9. The method of claim 7, wherein the access line corresponds to a data unit of the target data pattern having the first data value.

10. The method of claim 9, comprising repeating comparisons of data values of data units stored in memory cells coupled to additional access lines of the memory array that correspond to data units of the target data pattern that have the first data value.

11. The method of claim 10, comprising accumulating values from the repeated comparisons in sensing circuitry coupled to the memory array.

12. The method of claim 11, comprising inverting the accumulated values in sensing circuitry coupled to the memory array.

13. The method of claim 12, wherein comparing the number of data patterns comprises comparing a data value of each data unit of the data patterns stored in memory cells coupled to another access line to a second data value of the target data pattern that is different than the first data value.

14. The method of claim 13, wherein the second data value comprises a “

1”

.

15. The method of claim 13, wherein comparing the number of data patterns comprises comparing a data value of each data unit stored in memory cells coupled to another additional access line that corresponds to a data unit of the target data pattern that has the second data value.

16. The method of claim 13, comprising repeating comparisons of data values of data units of the data patterns stored in memory cells coupled to other additional access lines of the memory array that correspond to data units of the target data pattern that have the second data value.

17. The method of claim 16, wherein determining whether a data pattern matches the target data pattern comprises determining in the sensing circuitry, responsive to the act of comparing, whether a data pattern of the number of data patterns matches the target data pattern.

18. An apparatus, comprising:

an array of memory cells configured to store a data pattern in a number of memory cells coupled to a sense line;

sensing circuitry coupled to the array and controlled by a controller to cause;

comparing of a first data unit of a target data pattern to a first data unit of the stored data pattern by;

storing a first data value of the first data unit of the target data pattern in the compute component; and

logically ORing a data value of the first data unit of the stored first data pattern with the first data value stored in the compute component and store a result of the logical OR operation in the compute component,

wherein the first data unit of the stored data pattern and the first data unit of the target data pattern have a same data unit position;

comparing of a second data unit of the target data pattern to a second data unit of the stored data pattern by;

inverting of the result of the logical OR operation stored in the compute component; and

performing of a logical AND of the inverted result of the logical OR operation with a data value of the second data unit of the stored first data pattern and storing of a result of the logical AND operation in the compute component;

the second data unit of the target data pattern having a second data value, and wherein the second data unit of the stored data pattern and the second data unit of the target data pattern have a same data unit position; and

determining, based on the comparisons, whether the stored data pattern matches the target data pattern.

19. The apparatus of claim 18, wherein the stored data pattern is stored as a bit vector in the number of memory cells coupled to the sense line.

20. The apparatus of claim 19, wherein the sensing circuitry comprises a sense amplifier and a compute component corresponding to the sense line.

21. The apparatus of claim 20, wherein the compute component comprises a number of transistors formed on pitch with transistors of the sense amplifier.

22. The apparatus of claim 20, wherein the compute component comprises a number of transistors formed on pitch with the memory cells of the array.

23. The apparatus of claim 18, wherein the controller comprises an on-die controller.

24. The apparatus of claim 18, wherein the controller comprises control circuitry on a same semiconductor die as the memory array.

25. The apparatus of claim 18, wherein sensing circuitry further comprises a secondary sense amplifier and wherein the controller is further configured to cause the sensing circuitry to determine whether the stored data pattern matches the target data pattern by causing the second sense amplifier to sense the result of the logical AND operation stored in the compute component.

26. The apparatus of claim 18, wherein the sensing circuitry is further controlled by the controller to cause comparing of, for each of a number of additional data units of the target data pattern that have the first data value and a respective particular data unit position, the additional data unit of the target data pattern to an additional data unit of the stored data pattern at the respective particular data unit position.

27. The apparatus of claim 18, wherein the sensing circuitry is further controlled by the controller to cause comparing of, for each of a number of additional data units of the target data pattern that have the second data value and a respective particular data unit position, the additional data unit of the target data pattern to an additional data unit of the stored data pattern at the respective particular data unit position.

28. The apparatus of claim 18, wherein the sensing circuitry coupled to the array is further controlled by the controller to cause determining of, based on the comparisons, whether the stored data pattern matches the target data pattern by excluding comparisons from data units corresponding to masked data units of the target data pattern.

29. The apparatus of claim 18, further comprising a processing resource coupled to a memory device that includes the array of memory cells and the sensing circuitry.

30. An apparatus, comprising:

an array of memory cells configured to store a data pattern in a number of memory cells coupled to a sense line;

sensing circuitry coupled to the array of memory cells; and

a controller configured to control the sensing circuitry to;

compare a first data unit and a second data unit of a first set of data units of a target data pattern to a first data unit of the stored data pattern, wherein the first data unit of the stored data pattern corresponds to the first set of data units of the target data pattern;

store respective data values in the sensing circuitry that indicate whether each of the compared first and second data units of the target data pattern matches corresponding first data units of the stored data pattern;

invert the respective data values;

subsequently compare the respective inverted data values to a third data unit and a fourth data unit of a second set of data units of the target data pattern; and

determine, based on the comparisons, whether each of the subsequently compared data values matches the target data pattern.

31. The apparatus of claim 30, wherein, when the first data unit of the first set of data units include a first data value and the second data unit of the first set of data units includes a second data value, the first data unit of the stored data pattern is determined to match the target data pattern responsive to the first data unit of the stored data pattern including at least one of the first data value and the second data value.

32. The apparatus of claim 30, wherein, when the first data unit and the second data unit of the first set of data units include a same data value, the first data unit of the stored data pattern is determined to:

match the target data pattern if the first data unit of the stored data pattern includes the same data value; and

not match the target data pattern if the first data unit of the stored data pattern includes a different data value.

33. A method for comparing data patterns, comprising:

comparing, using a controller and sensing circuitry, a first data value to data values in data unit positions of a plurality of stored data patterns corresponding to data unit positions having the first data value in a target data pattern, wherein each stored data pattern of the plurality of stored data patterns is stored in memory cells coupled to a respective sense line;

storing respective data values in the sensing circuitry that indicate whether each of the compared data values matches;

inverting the data values stored in the sensing circuitry that indicate whether each of the compared data values matches;

subsequently comparing, using the controller and the sensing circuitry, the inverted data values stored in the sensing circuitry to data values in data unit positions of the plurality of stored data patterns corresponding to data unit positions having a second data value in the target data pattern; and

storing respective data values in the sensing circuitry that indicate whether each of the subsequently compared data values matches.

34. The method of claim 33, further comprising determining which, if any, of the data values stored in the sensing circuitry indicate a respective stored data pattern matches the target data pattern.

35. The method of claim 33, further comprising performing, using the controller and the sensing circuitry, a BlockOR operation to determine whether any data pattern of the plurality of stored data patterns matches the target data pattern.

36. The method of claim 35, wherein the BlockOR operation comprises:

charging an I/O line to a level corresponding to a data value that indicates none of the plurality of stored data patterns matches the target data pattern;

transferring the data values stored in the sensing circuitry that indicate whether each of the subsequently compared data values matches the data value on the I/O line; and

determining whether a level of the I/O line changes responsive to transferring the stored data values.