Semiconductor device and fabricating method thereof

• US 9,947,766 B2
• Filed: 07/10/2017
• Issued: 04/17/2018
• Est. Priority Date: 02/26/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiang, Tsung-Yu, Chen, Kuang-Hsin
• Primary Examiner(s): Blum, David S
• Application Number:
  US15/645,164
• Publication Number:
  US 20170309726A1
• Time in Patent Office: 281 Days
• Field of Search: 257301, 438306
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence

Abstract

A semiconductor device includes a substrate, a source/drain region, an etch stop layer, an oxide layer, an interlayer dielectric layer, and a contact plug. The source/drain region is in the substrate. The etch stop layer is over the source/drain region. The oxide layer is over the etch stop layer. The interlayer dielectric layer is over the oxide layer. The contact plug is electrically connected to the source/drain region through the interlayer dielectric layer, the oxide layer, and the etch stop layer.

Claims

1. A semiconductor device, comprising:

a substrate;

a source/drain region in the substrate;

an etch stop layer over the source/drain region;

an oxide layer over the etch stop layer;

an interlayer dielectric layer over the oxide layer; and

a contact plug electrically connected to the source/drain region through the interlayer dielectric layer, the oxide layer, and the etch stop layer.

2. The semiconductor device of claim 1, wherein the etch stop layer comprises a nitride material.

3. The semiconductor device of claim 1, further comprising a spacer on the substrate, wherein the etch stop layer has a portion on a sidewall of the spacer.

4. The semiconductor device of claim 3, wherein the contact plug is in contact with said portion of the etch stop layer on the sidewall of the spacer.

5. The semiconductor device of claim 1, further comprising:

a gate electrode over the substrate; and

an isolation layer over the gate electrode, wherein the contact plug is separated from the gate electrode by the isolation layer.

6. The semiconductor device of claim 5, wherein the contact plug is in contact with the isolation layer.

7. The semiconductor device of claim 1, wherein the oxide layer comprises SiON, SiOCN, SiO₂, or combinations thereof.

8. The semiconductor device of claim 1, wherein the interlayer dielectric layer comprises a flowable oxide.

9. A semiconductor device, comprising:

a substrate;

a gate structure over the substrate;

a source/drain region in the substrate and adjacent to the gate structure;

a nitride layer over the source/drain region;

a first oxide layer over the nitride layer;

a second oxide layer over the first oxide layer; and

a contact plug electrically connected to the source/drain region through the first oxide layer, the second oxide layer, and the nitride layer.

10. The semiconductor device of claim 9, wherein the gate structure comprises:

a gate electrode over the substrate; and

an isolation layer over the gate electrode, wherein the contact plug has a portion over and in contact with the isolation layer.

11. The semiconductor device of claim 10, wherein the nitride layer is thinner than the isolation layer.

12. The semiconductor device of claim 9, wherein a refractive index of the first oxide layer is different from a refractive index of the second oxide layer.

13. The semiconductor device of claim 9, wherein the first oxide layer is in contact with the nitride layer.

14. A method of fabricating semiconductor device comprising:

forming an etch stop layer over a source/drain region;

forming an oxide layer over the etch stop layer;

forming an interlayer dielectric layer over the oxide layer;

forming a contact opening through the interlayer dielectric layer, the oxide layer, and the etch stop layer to expose the source/drain region; and

forming a contact plug in the contact opening over the source/drain region.

15. The method of claim 14, further comprising annealing the interlayer dielectric layer with oxygen to densify the interlayer dielectric layer.

16. The method of claim 14, further comprising forming a gate structure over the substrate before forming the etch stop layer over the source/drain region.

17. The method of claim 16, wherein the etch stop layer is formed over the gate structure.

18. The method of claim 16, wherein the oxide layer is formed over the gate structure.

19. The method of claim 18, wherein forming the contact opening comprises removing a portion of the oxide layer over a sidewall of the gate structure.

20. The method of claim 18, wherein forming a contact opening comprises etching a portion of the gate structure.