Positive logic digitally tunable capacitor

  • US 9,948,281 B2
  • Filed: 09/02/2016
  • Issued: 04/17/2018
  • Est. Priority Date: 09/02/2016
  • Status: Active Grant
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First Claim
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1. An integrated circuit block comprising:

  • a first node;

    a second node;

    a resistive network;

    a series arrangement of two or more capacitors and a plurality of FET switches coupled between the first node and the second node; and

    supply rails providing a first supply voltage and a second supply voltage;

    wherein;

    a first capacitor of the two or more capacitors is coupled to the first node and a second capacitor of the two or more capacitors is coupled to the second node;

    the plurality of FET switches comprises a first end FET switch and a second end FET switch, the first end FET switch being closest to the first node and farthest from the second node and the second end FET switch being closest to the second node and farthest from the first node;

    each FET switch comprises a gate resistor connecting a FET switch gate to the first supply voltage;

    the resistive network comprises a plurality of resistive paths connecting the second supply voltage to drains of corresponding FET switches;

    the first supply voltage and the second supply voltage are non-negative supply voltages configured to enable or disable the FET switches and thereby adjusting the capacitance between the two nodes;

    the second supply voltage is a constant mid-rail voltage based on a threshold voltage of the plurality of FET switches; and

    the first supply voltage and the second supply voltage are independent of a number of FET switches of the plurality of the FET switches.

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