Semiconductor image sensor module and method of manufacturing the same

• US 9,955,097 B2
• Filed: 02/28/2014
• Issued: 04/24/2018
• Est. Priority Date: 06/02/2005
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Iwabuchi, Shin, Motoyoshi, Makoto
• Primary Examiner(s): LEE, JOHN R
• Application Number:
  US14/193,762
• Publication Number:
  US 20140175592A1
• Time in Patent Office: 1,516 Days
• Field of Search: 2502081, 348294, 348300, 348301, 348302, 348308, 438 66, 438 67, 438 73, 438 74, 438107, 438108, 438109, 257443, 257444, 257447, 257734, 257737, 257738, 257777, 257778, 257780, 257E31054, 257E21499, 257258, 257291
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/14607 Geometry of the photosensitive area
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 : Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 : MOS based technologies
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 29/788 : with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1425 : Converter
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/1443 : Non-volatile random-access memory [NVRAM]
• CPC Class Codes: H04N 23/54 : Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
• CPC Class Codes: H04N 25/75 : Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 : Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/79 : Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.

Claims

1. An image sensor comprising:

a first semiconductor part including a plurality of pixels arranged in a first array and an interlayer insulation film having multilayer wirings, respective ones of the pixels including a photoelectric conversion element disposed at a light-incident side of the first semiconductor part, wherein the interlayer insulation film is disposed below the photoelectric conversion element in a cross-section perspective, and disposed at a side of the first semiconductor part opposite to the light-incident side, and

a second semiconductor part including a plurality of analog/digital converters arranged in a second array; and

a third semiconductor part including a memory element array,

wherein the first, second, and third semiconductor parts are stacked and electrically connected to one another,

the first, second, and third semiconductor parts are electrically connected through a first contact portion and a second contact portion, and at least one of the first contact portion and the second contact portion is disposed through at least a portion of the first, second, and third semiconductor parts,

the first contact portion includes a first wiring part, a second wiring part, and a third wiring part that are electrically connected to one another, and

the first wiring part is disposed above a light-incident surface of the first semiconductor part in the cross-section perspective, the second wiring part is connected to the first wiring part and a wiring of the multilayer wirings, and the third wiring part is connected to the first wiring part, is not directly connected to the multilayer wirings, and is disposed through the first semiconductor part such that the first semiconductor part is electrically connected to the second semiconductor part.

2. The image sensor according to claim 1, wherein the first semiconductor part, the second semiconductor part, and the third semiconductor part are stacked in that order.

3. The image sensor according to claim 1, wherein

the image sensor is a back-illuminated image sensor, a first surface of the first semiconductor part being opposite from a second surface of the first semiconductor part, and the second surface of the first semiconductor part being on the light-incident side of the first semiconductor part.

4. The image sensor according to claim 3, wherein

the first surface of the first semiconductor part is coupled to a first surface of the second semiconductor part by a plurality of electroconductive connection bodies.

5. The image sensor according to claim 4, wherein

the electroconductive connection bodies include first pads formed on the first surface of the first semiconductor part, second pads formed on the first surface of the second semiconductor part, respective ones of the first pads corresponding positionally with respective ones of the second pads, and a bump formed between respectively corresponding first pads and second pads.

6. The image sensor according to claim 3, wherein

the first semiconductor part includes a transistor region formed toward the first surface of the first semiconductor part and a photodiode region formed toward the second surface of the first semiconductor part, the photodiode region including photodiodes corresponding to respective ones of the plurality of pixels and the transistor region including transistors corresponding to respective ones of the photodiodes.

7. The image sensor according to claim 1, wherein

the plurality of pixels are arranged into a plurality of pixel array blocks, and

respective ones of the plurality of analog/digital converters correspond to respective ones of the plurality of pixel array blocks.

8. The image sensor according to claim 1, wherein a first surface of the first semiconductor part is laminated to a first surface of the second semiconductor part.

9. The image sensor according to claim 1, wherein a first surface of the first semiconductor part is bonded to a first surface of the second semiconductor part with an adhesive material.

10. The image sensor according to claim 1, wherein the first and second semiconductor parts are arranged close to the third semiconductor part such that a plurality of photoelectric conversion elements and a plurality of memory elements share one analog/digital converter.

11. The image sensor according to claim 10, wherein each of the memory elements is a volatile memory.

12. The image sensor according to claim 10, wherein each of the memory elements is a floating gate nonvolatile memory.

13. The image sensor according to claim 10, wherein each of the memory elements is an MONOS nonvolatile memory.

14. The image sensor according to claim 10, wherein each of the memory elements is a multivalued nonvolatile memory.

21. The image sensor according to claim 1, wherein a material of the first contact portion is the same at both a respective first surface of the corresponding at least one of the first, second, and third semiconductor parts and a respective second surface of the corresponding at least one of the first, second, and third semiconductor parts.

15. A method of making an image sensor module, comprising the steps of:

forming a first semiconductor part, the first semiconductor part including a plurality of pixels arranged in a first array and an interlayer insulation film having multilayer wirings, respective ones of the pixels including a photoelectric conversion element disposed at a light-incident side of the first semiconductor part, wherein the interlayer insulation film is disposed below the photoelectric conversion element in a cross-section perspective, and disposed at a side of the first semiconductor part opposite to the light-incident side;

forming a second semiconductor part, the second semiconductor part including a plurality of analog/digital converters arranged in a second array;

forming a third semiconductor part, the third semiconductor part including a memory element array; and

stacking and electrically connecting the first, second, and third semiconductor parts to one another,

wherein the first, second, and third semiconductor parts are electrically connected through a first contact portion and a second contact portion, and at least one of the first contact portion and the second contact portion is disposed through at least a portion of the first, second, and third semiconductor parts and extending from a respective first surface of the corresponding at least one of the first, second, and third semiconductor parts,

the first contact portion includes a first wiring part, a second wiring part, and a third wiring part that are electrically connected to one another, and

the first wiring part is disposed above a light-incident surface of the first semiconductor part in the cross-section perspective, the second wiring part is connected to the first wiring part and a wiring of the multilayer wirings, and the third wiring part is connected to the first wiring part, is not directly connected to the multilayer wirings, and is disposed through the first semiconductor part such that the first semiconductor part is electrically connected to the second semiconductor part.

16. The method according to claim 15, further comprising:

stacking the first semiconductor part, the second semiconductor part, and the third semiconductor part in that order.

17. The method according to claim 15, further comprising:

laminating the first semiconductor part to the second semiconductor part.

18. The method according to claim 15, further comprising:

bonding a first surface of the first semiconductor part to a first surface of the second semiconductor part.

19. The method according to claim 18, further comprising:

forming first pads on the first surface of the first semiconductor part and forming second pads on the first surface of the second semiconductor part, respective ones of the first pads corresponding positionally with respective ones of the second pads, and

forming a bump between respectively corresponding first pads and second pads.

20. The method according to claim 15, further comprising:

connecting respective ones of the plurality of pixels with a corresponding one of the plurality of analog/digital converters by a through-hole that passes through a wafer.