Stacked PA power control

• US 9,960,737 B1
• Filed: 03/06/2017
• Issued: 05/01/2018
• Est. Priority Date: 03/06/2017
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Kovac, David
• Primary Examiner(s): Choe, Henry
• Application Number:
  US15/451,184
• Time in Patent Office: 421 Days
• Field of Search: 330311, 330310
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: H03F 1/0222 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0266 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/375 Circuitry to compensate the offset being present in an amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/555 A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 2200/61 the cascode amplifier has more than one common gate stage
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/21 with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03G 1/0023 in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03G 1/007 using FET type devices

Abstract

Systems, methods and apparatus for efficient power control of an RF amplifier for amplification of a constant envelope RF signal are described. A reduction in a size of a pass device of an LDO regulator is obtained by removing the pass device of the LDO regulator from a main current conduction path of the RF amplifier. Power control is provided by varying one or more gate voltages to cascoded transistors of a transistor stack of the RF amplifier according to a power control voltage. Various configurations for controlling the gate voltages are presented by way of a smaller size LDO regulator or by completely removing the LDO regulator. In a case where a supply voltage to the transistor stack varies, such as in a case of a battery, a compensation circuit is used to adjust the power control voltage in view of a variation of the supply voltage, and therefore null a corresponding drift in output power of the RF amplifier.

Claims

1. A circuital arrangement comprising:

a stack of a plurality of transistors arranged in a cascode configuration, comprising;

(i) an input transistor adapted to receive an input radio frequency (RF) signal; and

(ii) one or more cascoded transistors, the one or more cascoded transistors comprising an output transistor adapted to output, at an adjustable output power, an output RF signal based on the input RF signal;

a first resistor tree comprising a plurality of series connected resistors; and

a low dropout (LDO) regulator coupled to the first resistor tree,

wherein;

the adjustable output power is controlled by varying at least one gate voltage of the one or more cascoded transistors of the stack,

a node of the first resistor tree is configured to provide the at least one gate voltage, and

a control voltage to the LDO regulator varies the at least one gate voltage to provide the adjustable output power from the stack.

2. The circuital arrangement according to claim 1, further comprising one or more gate capacitors each connected between a gate of a transistor of the one or more cascoded transistors and a reference potential, wherein the each gate capacitor is configured to allow a gate voltage at the gate to vary along with an RF voltage at a drain of the transistor.

3. The circuital arrangement according to claim 2, wherein the one or more gate capacitors are configured to substantially equalize an RF voltage of the output RF signal at a drain of the output transistor across the plurality of transistors of the stack.

4. The circuital arrangement according to claim 2, wherein:

the input RF signal is a constant envelope input RF signal, and

the circuital arrangement is adapted to amplify the constant envelope input RF signal and generate the output RF signal as an amplified version of the input RF signal at a drain terminal of the output transistor according to the adjustable output power.

5. The circuital arrangement according to claim 1, wherein the at least one gate voltage comprises two or more gate voltages of the one or more cascoded transistors.

6. The circuital arrangement according to claim 1, wherein the at least one gate voltage comprises a gate voltage of the output transistor.

7. The circuital arrangement according to claim 1, wherein the at least one gate voltage comprises a gate voltage of a transistor of the one or more cascoded transistors that is directly coupled to the input transistor.

8. The circuital arrangement according to claim 1, further comprising:

a second resistor tree comprising a plurality of series connected resistors,

wherein;

the second resistor tree is configured to provide fixed voltages to remaining gate voltages of the one or more transistors of the cascoded transistors of the stack based on a fixed regulated voltage.

15. The circuital arrangement according to claim 1, wherein the plurality of transistors are metal-oxide-semiconductor (MOS) field effect transistors (FETs), or complementary metal-oxide-semiconductor (CMOS) field effect transistors (FETs).

16. The circuital arrangement according to claim 15, wherein the plurality of transistors are fabricated using one of:

a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS).

17. The circuital arrangement according to claim 1, wherein the circuital arrangement is adapted to operate as an RF power amplifier for a GSM system.

18. The circuital arrangement according to claim 1, wherein a supply voltage to the stack is a substantially fixed supply voltage.

19. The circuital arrangement according to claim 18, wherein the substantially fixed supply voltage is a battery voltage.

20. The circuital arrangement according to claim 1, wherein a dynamic range of the adjustable output power is larger than 50 dB.

21. The circuital arrangement according to claim 20, wherein the dynamic range of the adjustable output power is larger than about 60 dB.

22. The circuital arrangement according to claim 1, wherein:

a supply voltage to the stack is a varying supply voltage, and

a drift of the adjustable output power with respect to the varying supply voltage is compensated for by further varying the at least one gate voltage according to a variable voltage level of the varying supply voltage.

9. A circuital arrangement comprising:

a stack of a plurality of transistors arranged in a cascode configuration, comprising;

(i) an input transistor adapted to receive an input radio frequency (RF) signal; and

(ii) one or more cascoded transistors, the one or more cascoded transistors comprising an output transistor adapted to output, at an adjustable output power, an output RF signal based on the input RF signal; and

a gate voltage control module coupled to gates of the one or more transistors of the stack,

wherein;

the adjustable output power is controlled by varying at least one gate voltage of the one or more cascoded transistors of the stack, and

the gate voltage control module is configured to provide, based on a control voltage, the at least one gate voltage independently from remaining gate voltages of the one or more transistors of the cascoded transistors of the stack.

10. The circuital arrangement according to claim 9, wherein the gate voltage control module is further configured to provide fixed voltages to remaining gate voltages of the one or more transistors of the cascoded transistors of the stack.

11. The circuital arrangement according to claim 10, wherein the gate voltage control module further comprises a configuration control module configured to control association of the at least one gate voltage and the fixed voltages to the gates of the one or more transistors of the stack based on configuration control data.

12. The circuital arrangement according to claim 11, wherein the configuration control module comprises a lookup table adapted to store the configuration control data.

13. The circuital arrangement according to claim 12, wherein the configuration control data are in correspondence of one or more performance profiles of the circuital arrangement.

14. The circuital arrangement according to claim 12, wherein the one or more performance profiles comprises:

a) a linearity performance, and b) a dynamic range performance.

23. A method for controlling an output power of an amplifier arrangement, the method comprising:

providing a stack of a plurality of transistors arranged in a cascode configuration, comprising an input transistor and one or more cascoded transistors, the one or more cascoded transistors comprising an output transistor;

providing a first resistor tree comprising a plurality of series connected resistors and a low dropout (LDO) regulator coupled to the first resistor tree;

supplying a supply voltage across the stack;

providing gate voltages to the one or more cascoded transistors;

inputting a constant envelope radio frequency (RF) signal to the input transistor;

based on the inputting, obtaining an amplified RF signal at the output transistor;

varying at least one gate voltage of the gate voltages to the one or more cascoded transistors; and

based on the varying, controlling the output power of the amplified RF signal,

wherein a node of the first resistor tree is configured to provide the at least one gate voltage, and

wherein a control voltage to the LDO regulator varies the at least one gate voltage for controlling of the output power of the amplified RF signal.

24. The method according to claim 23, further comprising:

based on the varying, varying a transconductance of the stack.

25. The method according to claim 23, further comprising:

based on the varying, varying an ON resistance of a transistor of the one or more cascoded transistors.

26. The method according to claim 23, further comprising:

based on the varying, changing a region of operation of a transistor of the one or more cascoded transistors from a saturation region of operation to a triode region of operation, or vice versa.

27. The method according to claim 23, further comprising:

coupling gate capacitors to gates of the one or more cascoded transistors; and

based on the coupling, providing a substantial equal division of the amplified RF signal across the plurality of the transistors of the stack.

28. The method according to claim 23, further comprising:

based on the varying, limiting a voltage across any two terminals of the input transistor and

based on the limiting, reducing a hot carrier injection (HCI) effect of the input transistor.

29. The method according to claim 23, wherein the supply voltage is a varying supply voltage, the method further comprising:

determining a voltage level of the supply voltage;

based on the determining, further varying the at least one gate voltage; and

based on the further varying, maintaining the output power of the amplified RF signal.

30. The method according to claim 23, wherein the controlling of the output power of the amplified RF signal provides a dynamic range of the output power greater than 50 dB.