Radio-frequency devices with gate node voltage compensation

• US 9,973,184 B2
• Filed: 01/20/2016
• Issued: 05/15/2018
• Est. Priority Date: 07/07/2012
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Madan, Anuj, Altunkilic, Fikret, Blin, Guillaume Alexandre
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): O TOOLE, COLLEEN J
• Application Number:
  US15/002,170
• Publication Number:
  US 20160134270A1
• Time in Patent Office: 846 Days
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15184 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H03K 17/06 Modifications for ensuring a fully conducting state
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H04B 1/40 : Circuits

Abstract

Radio-frequency (RF) devices are disclosed having transistor gate voltage compensation to provide improved switching performance. RF devices, such as switches, include a plurality of field-effect transistors (FETs) connected in series between first and second nodes, each FET having a gate. A compensation network including a coupling circuit couples the gates of each pair of neighboring FETs.

Claims

1. A semiconductor die comprising:

a semiconductor substrate;

a first field-effect transistor formed on the semiconductor substrate and including a first gate node;

a second field-effect transistor connected in series with the first field-effect transistor and including a second gate node;

a third field-effect transistor connected in series with the second field-effect transistor and including a third gate node;

a first capacitor that is directly connected at a first end to the first gate node, directly connected at a second end to the second gate node, and configured to block DC current flow between the first gate node and the second gate node; and

a second capacitor that is directly connected at a first end to the second gate node, directly connected at a second end to the third gate node, and configured to block DC current flow between the second gate node and the third gate node.

2. The semiconductor die of claim 1 wherein the first and second field-effect transistors are silicon-on-insulator field-effect transistors.

3. The semiconductor die of claim 1 wherein the first capacitor, second capacitor and a resistor are part of a compensation network configured to reduce voltage swings across each of the first and second field-effect transistors.

4. The semiconductor die of claim 1 further comprising a feed-forward circuit that couples a source of the first field-effect transistor to the first gate node.

5. The semiconductor die of claim 4 wherein the feed-forward circuit includes a third capacitor.

6. The semiconductor die of claim 5 wherein the feed-forward circuit further includes a resistor connected in series with the third capacitor.

7. The semiconductor die of claim 1 wherein the first capacitor has a higher capacitance value than the second capacitor.

8. The semiconductor die of claim 1 wherein the first, second and third gate nodes are coupled to a gate bias voltage node.

9. The semiconductor die of claim 1 further comprising a body bias network connected to, and configured to provide body bias signals to, body nodes of the first, second and third field-effect transistors.

10. The semiconductor die of claim 9 wherein the body bias network is configured so that each of the first, second and third field-effect transistors receives a common body bias signal.

11. A method for operating a radio-frequency device, the method comprising:

controlling first, second and third field-effect transistors connected in series between first and second nodes so that the first, second and third field-effect transistors are collectively in an ON state or an OFF state;

blocking DC current flow between a first gate node of the first field-effect transistor and a second gate node of the second field-effect transistor using a first capacitor that is directly connected at a first end to the first gate node and directly connected at a second end to the second gate node; and

blocking DC current flow between the second gate node and a third gate node of the third field-effect transistor using a second capacitor that is directly connected at a first end to the second gate node and directly connected at a second end to the third gate node.

12. The method of claim 11 further comprising receiving a radio-frequency signal having a power value at the first node and outputting the radio-frequency signal at the second node when the first field-effect transistor is in the ON state.

13. A wireless device comprising:

a transceiver configured to process radio-frequency signals;

an antenna in communication with the transceiver configured to facilitate transmission of an amplified radio-frequency signal;

a power amplifier connected to the transceiver and configured to generate the amplified radio-frequency signal; and

a switch connected to the antenna and the power amplifier and configured to selectively route the amplified radio-frequency signal to the antenna, the switch including a first field-effect transistor including a first gate node, a second field-effect transistor connected in series with the first field-effect transistor and including a second gate node, and a third field-effect transistor connected in series with the second field-effect transistor and including a third gate node, the switch further including a first capacitor that is directly connected at a first end to the first gate node, directly connected at a second end to the second gate node, and configured to block DC current flow between the first gate node and the second gate node, the switch further including a second capacitor that is directly connected at a first end to the second gate node and directly connected at a second end to the third gate node.

14. The wireless device of claim 13 wherein the switch is formed on a silicon-on-insulator die of the wireless device.

15. The wireless device of claim 13 wherein the switch is part of a receive path, the switch being connected to an output node for a radio-frequency signal received from the antenna.