Stacked semiconductor structure and method of forming the same

• US 9,975,762 B2
• Filed: 06/12/2013
• Issued: 05/22/2018
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chu, Chia-Hua, Cheng, Chun-Wen
• Primary Examiner(s): Payen, Marvin
• Assistant Examiner(s): Webb, Vernon P
• Application Number:
  US13/916,148
• Publication Number:
  US 20150251895A1
• Time in Patent Office: 1,805 Days
• Field of Search: 257595, 438107
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure

Abstract

A stacked semiconductor structure includes a first substrate. A multilayer interconnect is disposed over the first substrate. Metal sections are disposed over the multilayer interconnect. First bonding features are over the metal sections. A second substrate has a front surface. A cavity extends from the front surface into a depth D in the second substrate. A movable structure is disposed over the front surface of the second substrate and suspending over the cavity. The movable structure includes a dielectric membrane, metal units over the dielectric membrane and a cap dielectric layer over the metal units. Second bonding features are over the cap dielectric layer and bonded to the first bonding features. The second bonding features extend through the cap dielectric layer and electrically coupled to the metal units.

Claims

1. A stacked semiconductor structure comprising:

a first substrate having at least one transistor disposed over the first substrate;

a multilayer interconnect disposed over the at least one transistor and electrically coupled to the at least one transistor;

metal sections disposed over the multilayer interconnect;

first bonding features over the metal sections;

a second substrate having a bottom surface, the second substrate comprising silicon or germanium;

a first dielectric layer disposed on the bottom surface of the second substrate;

a cavity extending from a surface of the first dielectric layer into a depth D of the silicon or germanium of the second substrate, wherein top and side surfaces of the cavity comprise the silicon or germanium of the second substrate;

a movable structure as a continuous unit disposed between the second substrate and the multilayer interconnect, the movable structure including a first portion of a cap dielectric layer, a first portion of a metal units layer in contact with the first portion of the cap dielectric layer, and a dielectric membrane in contact with the first portion of the metal units layer; and

second bonding features on a second portion of the cap dielectric layer, the second bonding features bonded to the first bonding features, wherein the second bonding features extend through the second portion of the cap dielectric layer and electrically connect to a second portion of the metal units layer.

2. The stacked semiconductor structure of claim 1, wherein the movable structure further comprises metal segments on the dielectric membrane opposite to the first portion of the metal units layer, the metal segments being interposed between the dielectric membrane and the second substrate.

3. The stacked semiconductor structure of claim 2, wherein the movable structure further comprises the first dielectric layer between the metal segments and the second substrate.

4. The stacked semiconductor structure of claim 1, wherein the first portions of the metal units layer of the movable structure and portions of the metal sections construct a micro-machined capacitor with a variable capacitance.

5. The stacked semiconductor structure of claim 1, wherein the first substrate has a width W₂ wider than a width W₁ of the second substrate.

6. The stacked semiconductor structure of claim 1, further comprising:

through substrate vias (TSVs) extending from a top surface of the second substrate through the second substrate to electrically connect to the second portion of the metal units layer.

7. The stacked semiconductor structure of claim 1, further comprising:

a seal ring composed of a portion of the bonded first bonding features and second bonding features, wherein the seal ring surrounds the first portion of the metal units layer and the metal sections.

8. The stacked semiconductor structure of claim 1, wherein a ratio of a thickness of the dielectric membrane to a thickness of the first portion of the metal units layer is in a range from about 2 to about 7.

9. The stacked semiconductor structure of claim 1, wherein the first portion of the metal units layer and the metal sections include at least one signal element and at least one pull-down element adjacent to the at least one signal element, the at least one signal element and the at least one pull-down element separated by a gap.

10. The stacked semiconductor structure of claim 9 further comprising a dielectric bump disposed over the at least one pull-down element of the metal sections.

11. A stacked semiconductor structure comprising:

a CMOS device, the CMOS device comprising;

a first substrate;

a multilayer interconnect disposed over the first substrate;

a bottom electrode disposed over the multilayer interconnect, the bottom electrode comprising a first segment and a second segment;

a protection dielectric layer disposed over and in contact with the bottom electrode, the protection dielectric layer having a first extension extending vertically further from the first segment of the bottom electrode than vertically from the second segment of the bottom electrode; and

first bonding features over the bottom electrode; and

a MEMS device, the MEMS device comprising;

a second substrate having a lower surface;

a cavity extending upward from the lower surface into a depth D in the second substrate, surfaces of the cavity within the depth D comprising silicon or germanium substrate material;

a flexible dielectric membrane interposed between the second substrate and the CMOS device and suspended under the cavity, the flexible dielectric membrane having a thickness in a range from about 0.5 micrometers to about 5 micrometers;

a top electrode disposed on the flexible dielectric membrane;

a cap dielectric layer disposed on the top electrode; and

second bonding features interposed between the cap dielectric layer and the first bonding features, the second bonding features bonded to the first bonding features, wherein the top electrode and the bottom electrode construct a capacitor having a variable capacitance.

12. The stacked semiconductor structure of claim 11, further comprising metal segments on the flexible dielectric membrane opposite to the top electrode, and the metal segments being between the flexible dielectric membrane and the second substrate.

13. The stacked semiconductor structure of claim 12, further comprising a dielectric layer between the metal segments and the second substrate.

14. The stacked semiconductor structure of claim 11, further comprising a seal ring composed of a portion of the bonded first bonding features and second bonding features, the seal ring surrounding the top electrode and the bottom electrode.

15. The stacked semiconductor structure of claim 11, wherein a ratio of a thickness of the flexible dielectric membrane to a thickness of the top electrode is in a range from about 2 to about 7.

16. The stacked semiconductor structure of claim 11, further comprising a dielectric bump disposed over the first segment of the bottom electrode and under the protection dielectric layer.

17. The stacked semiconductor structure of claim 11, wherein each of the top electrode and the bottom electrode comprises aluminum, copper, aluminum/copper alloy, titanium, tantalum, tungsten, metal silicide, or combinations thereof.

18. A stacked semiconductor structure comprising:

a first substrate having a front surface;

a first dielectric layer disposed on the first substrate;

a plurality of metal segments disposed on the first dielectric layer;

a dielectric membrane on the first dielectric layer and the plurality of metal segments, the dielectric membrane comprising at least one opening exposing at least a portion of one of the plurality of metal segments;

a plurality of metal units disposed on the dielectric membrane and on a bottom surface and sidewalls of the at least one opening;

a cap dielectric layer disposed over the dielectric membrane and the plurality of metal units, the cap dielectric layer comprising at least one via disposed therein, the via exposing a portion of one of the plurality of metal units;

a first connection feature disposed over the via and electrically connected to the exposed portion of the one of the plurality of metal units;

a moveable unit comprising;

a first portion of the first dielectric layer,

a first portion of the plurality of metal segments disposed on the first portion of the first dielectric layer,

a first portion of the dielectric membrane disposed on the first portion of the first dielectric layer and the first portion of the plurality of metal segments,

a first portion of the plurality of metal units disposed on the first portion of the dielectric membrane, and

a first portion of the cap dielectric layer disposed over the first portion of the dielectric membrane and first portion of the plurality of metal units;

a first cavity extending from the front surface of the first substrate into a depth D in the first substrate, the first cavity extending laterally under a portion of the first dielectric layer;

a CMOS device comprising a second connection feature disposed on a first surface of the CMOS device, the second connection feature being bonded to the first connection feature; and

a second cavity comprising the first cavity and a space formed between the CMOS device and the cap dielectric layer, the moveable unit suspended in the second cavity.

19. The stacked semiconductor structure of claim 18, wherein the CMOS device further comprises:

a multilayer interconnect interposed between the first substrate and a second substrate;

metal sections interposed between the multilayer interconnect and the first substrate;

a second dielectric layer on the metal sections and the multilayer interconnect, openings in the second dielectric layer exposing at least a portion of the metal sections;

a protection dielectric on the second dielectric layer and the metal sections; and

an aperture in the protection dielectric and the second dielectric layer, the aperture exposing a portion of the metal sections, the second connection feature disposed on the protection dielectric and within the aperture.

20. The stacked semiconductor structure of claim 18, further comprising recesses in the first substrate at each end of the first substrate, the recesses extending under a portion of the first dielectric layer.