Apparatus and method for memory-hierarchy aware producer-consumer instruction

• US 9,990,287 B2
• Filed: 12/21/2011
• Issued: 06/05/2018
• Est. Priority Date: 12/21/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Raikin, Shlomo, Sade, Raanan, Valentine, Robert, Mandelblat, Julius Yuli, Shalev, Ron, Novakovsky, Larisa
• Primary Examiner(s): Mazumder, Saptarshi
• Application Number:
  US13/994,122
• Publication Number:
  US 20140192069A1
• Time in Patent Office: 2,358 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3881 Arrangements for communication of instructions and data
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.

Claims

1. A method for transferring a chunk of data from a core of a central processing unit (CPU) to a graphics processing unit (GPU), comprising:

executing a first instruction, the first instruction being a single instruction, wherein the first instruction comprises a MovNonAllocate store instruction, the executing comprising;

responsive to the first instruction,

writing data, without caching the data, to a buffer within the core of the CPU until a designated amount of data has been written, wherein the buffer combines multiple stores until the designated amount of data has been written, and

upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache shared by both the core and the GPU, wherein the cache is a level 3 cache;

setting an indication to indicate to the GPU that data is available in the cache; and

upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.

2. The method as in claim 1 wherein the indication comprises a flag writable by the core and readable by the GPU.

3. The method as in claim 2 wherein the flag comprises a binary value indicative having a first value indicating that the data is available in the cache and a second value indicating that data is not available in the cache.

4. The method as in claim 1 wherein the GPU reads the indication via a polling technique in which the GPU periodically reads polls for the indication.

5. The method as in claim 1 wherein the GPU reads the indication in response to an interrupt signal.

6. The method as in claim 1 further comprising:

permitting the first instruction to be interleaved with a plurality of other instructions of the same instruction type.

7. The method as in claim 1 further comprising:

permitting the first instruction to be interleaved with a plurality of other instructions of different instruction types.

8. The method as in claim 7 wherein the other instructions are write-back store instructions.

9. The method as in claim 1 wherein the buffer within the CPU is a write-back buffer.

10. The method as in claim 1 wherein the CPU comprises a plurality of cores, each capable of performing the method.

11. An instruction processing apparatus comprising:

at least one core of a central processing unit (CPU) and a cache shared by both the core and a graphics processing unit (GPU); and

the core comprising CPU-GPU producer-consumer logic configured to perform the operations of;

executing a first instruction, the first instruction being a single instruction, wherein the first instruction comprises a MovNonAllocate store instruction, the executing comprising;

writing data, without caching the data, to a buffer within the core of the CPU until a designated amount of data has been written, wherein the buffer combines multiple stores until the designated amount of data has been written, and

upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to the cache shared by both the core and the GPU, wherein the cache is a level 3 cache; and

setting an indication to indicate to the GPU that data is available in the cache;

wherein upon the GPU detecting the indication, the data is provided to the GPU from the cache upon receipt of a read signal from the GPU.

12. The instruction processing apparatus as in claim 11 wherein the indication comprises a flag writable by the core and readable by the GPU.

13. The instruction processing apparatus as in claim 12 wherein the flag comprises a binary value indicative having a first value indicating that the data is available in the cache and a second value indicating that data is not available in the cache.

14. The instruction processing apparatus as in claim 11 wherein the GPU reads the indication via a polling technique in which the GPU periodically reads polls for the indication.

15. The instruction processing apparatus as in claim 11 wherein the GPU reads the indication in response to an interrupt signal.

16. The instruction processing apparatus as in claim 11 wherein the CPU-GPU producer-consumer logic permits the first instruction to be interleaved with a plurality of other instructions of the same instruction type.

17. The instruction processing apparatus as in claim 11 wherein the CPU-GPU producer-consumer logic permits the first instruction to be interleaved with a plurality of other instructions of different instruction types.

18. The instruction processing apparatus as in claim 17 wherein the other instructions are write-back store instructions.

19. The instruction processing apparatus as in claim 11 wherein the buffer within the CPU is a write-back buffer.

20. The instruction processing apparatus as in claim 11 wherein the CPU comprises a plurality of cores, each having CPU-GPU producer-consumer logic for performing the specified operations.

21. A computer system comprising:

a graphics processor unit (GPU) for processing a set of graphics instructions to render video; and

a central processing unit (CPU) comprising;

at least one core and a cache shared by both the core and the GPU; and

the core comprising CPU-GPU producer-consumer logic configured to perform the operations of;

executing a first instruction, the first instruction being a single instruction, wherein the first instruction comprises a MovNonAllocate store instruction, the executing comprising;

writing data to a buffer within the core of the CPU until a designated amount of data has been written, wherein the buffer combines multiple stores until the designated amount of data has been written, and

upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to the cache shared by both the core and the GPU, wherein the cache is a level 3 cache; and

setting an indication to indicate to the GPU that data is available in the cache;

wherein upon the GPU detecting the indication, the data is provided to the GPU from the cache upon receipt of a read signal from the GPU.