Chemical sensor with sidewall spacer sensor surface

• US 9,995,708 B2
• Filed: 11/17/2014
• Issued: 06/12/2018
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Fife, Keith G., Bustillo, James, Owens, Jordan
• Primary Examiner(s): ARMAND, MARC ANTHONY
• Application Number:
  US14/543,551
• Publication Number:
  US 20150064829A1
• Time in Patent Office: 1,303 Days
• Field of Search: 257253, 438 49
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors

Abstract

In one implementation, a chemical sensor is described. The chemical sensor includes chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A dielectric material defines an opening extending to the upper surface of the floating gate conductor. A conductive sidewall spacer is on a sidewall of the opening and contacts the upper surface of the floating gate conductor.

Claims

1. A method for manufacturing a chemical sensor, the method comprising:

forming a chemically-sensitive field effect transistor including a floating gate conductor having an upper surface;

forming a dielectric material defining an opening extending to the upper surface of the floating gate conductor;

forming a conductive sidewall spacer on a sidewall of the opening and contacting the floating gate conductor; and

oxidizing an inner surface of the conductive sidewall spacer.

2. The method of claim 1, wherein forming the conductive sidewall spacer comprises:

depositing a conductive material within the opening;

etching the conductive material to expose the upper surface of the floating gate conductor.

3. The method of claim 1, wherein:

depositing the conductive material includes depositing the conductive material on an upper surface of the dielectric material; and

etching the conductive material exposes the upper surface of the dielectric material.

4. The method of claim 1, wherein the conductive sidewall spacer includes an inner surface surrounding a reaction region for the chemical sensor.

5. The method of claim 4, wherein the inner surface of the conductive sidewall spacer is an outer surface of the reaction region, and the upper surface of the floating gate conductor is a bottom surface of the reaction region.

6. The method of claim 1, wherein the conductive sidewall spacer comprises an electrically conductive material, and an inner surface of the conductive sidewall spacer includes an oxide of the electrically conductive material.

7. The method of claim 1, wherein a sensing surface for the chemical sensor includes an inner surface of the conductive sidewall spacer and the upper surface of the floating gate conductor.

8. The method of claim 7, wherein the sensing surface is sensitive to hydrogen ions.

9. The method of claim 1, wherein the conductive sidewall spacer comprises material different from material at the upper surface of the floating gate conductor.

10. The method of claim 1, wherein the conductive sidewall spacer includes titanium nitride or titanium.

11. The method of claim 1, wherein the floating gate conductor includes titanium nitride or titanium.

12. The method of claim 11, wherein the conductive sidewall spacer includes hafnium.

13. The method of claim 1, wherein oxidizing including forming titanium oxide or titanium oxynitride.

14. The method of claim 2, wherein depositing the conductive material includes depositing a conformal layer of the conductive material.

15. The method of claim 2, wherein depositing the conductive material includes atomic layer deposition (ALD).

16. The method of claim 2, wherein depositing the conductive material includes chemical vapor deposition (CVD).

17. The method of claim 2, wherein etching the conductive material includes anisotropic etching.

18. The method of claim 2, wherein anisotropic etching includes plasma etching.

19. The method of claim 2, wherein anisotropic etching includes reactive ion etching (RIE).

20. The method of claim 3, wherein depositing the conductive material includes depositing a conformal layer of the conductive material.