Semiconductor device and manufacturing method thereof

• US 9,997,638 B2
• Filed: 05/18/2017
• Issued: 06/12/2018
• Est. Priority Date: 02/27/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Godo, Hiromichi, Akimoto, Kengo, Yamazaki, Shunpei
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US15/598,683
• Publication Number:
  US 20170256650A1
• Time in Patent Office: 390 Days
• Field of Search: 257 43, 257 64, 257 59, 257 72, 257E21476, 257E21459, 257E21746, 438104, 438158, 438 85, 438 86
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current. The thin film transistor using an oxide semiconductor layer is formed by stacking an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer so that the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the oxide semiconductor layer containing insulating oxide interposed therebetween; whereby, variation in threshold voltage of the thin film transistors can be reduced and thus the electric characteristics can be stabilized. Further, an off current can be reduced.

Claims

1. A semiconductor device comprising:

a gate electrode layer including copper;

a gate insulating layer over the gate electrode layer, the gate insulating layer including silicon and oxygen;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer comprising a channel formation region, the oxide semiconductor layer including indium, gallium, zinc and oxygen; and

source and drain electrode layers electrically connected to the oxide semiconductor layer, the source and drain electrode layers including copper,

wherein the gate electrode layer has a layered structure,

wherein the gate insulating layer has a layered structure, and

wherein the channel formation region includes a crystal grain which is 1 nm to 10 nm in diameter.

2. The semiconductor device according to claim 1, further comprising an insulating layer over the source and drain electrode layers,

wherein the insulating layer is in contact with an upper surface of the oxide semiconductor layer between the source and drain electrode layers.

3. The semiconductor device according to claim 1, further comprising an insulating layer over at least the channel formation region of the oxide semiconductor layer,

wherein the source and drain electrode layers are over the insulating layer.

4. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer, the gate insulating layer including silicon and oxygen;

a first oxide semiconductor layer over the gate insulating layer, the first oxide semiconductor layer comprising a channel formation region;

a second oxide semiconductor layer over the first oxide semiconductor layer, each of the first oxide semiconductor layer and the second oxide semiconductor layer including indium, gallium, zinc and oxygen; and

source and drain electrode layers electrically connected to the second oxide semiconductor layer, the source and drain electrode layers including copper,

wherein the gate electrode layer has a layered structure,

wherein the gate insulating layer has a layered structure, and

wherein the channel formation region includes a crystal grain which is 1 nm to 10 nm in diameter.

5. The semiconductor device according to claim 4, further comprising an insulating layer over the source and drain electrode layers,

wherein the insulating layer is in contact with an upper surface of the second oxide semiconductor layer between the source and drain electrode layers.

6. The semiconductor device according to claim 4, further comprising an insulating layer over at least the channel formation region of the second oxide semiconductor layer,

wherein the source and drain electrode layers are over the insulating layer.

7. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer, the gate insulating layer including silicon and oxygen;

a first oxide semiconductor layer over the gate insulating layer, the first oxide semiconductor layer comprising a channel formation region;

a second oxide semiconductor layer over the first oxide semiconductor layer, each of the first oxide semiconductor layer and the second oxide semiconductor layer including indium, gallium, zinc and oxygen; and

source and drain electrode layers electrically connected to the second oxide semiconductor layer, the source and drain electrode layers including copper,

wherein a conductance of the first oxide semiconductor layer is higher than that of the second oxide semiconductor layer,

wherein the gate electrode layer has a layered structure,

wherein the gate insulating layer has a layered structure, and

wherein the channel formation region includes a crystal grain which is 1 nm to 10 nm in diameter.

8. The semiconductor device according to claim 7, further comprising an insulating layer over the source and drain electrode layers,

wherein the insulating layer is in contact with an upper surface of the second oxide semiconductor layer between the source and drain electrode layers.

9. The semiconductor device according to claim 7, further comprising an insulating layer over at least the channel formation region of the second oxide semiconductor layer,

wherein the source and drain electrode layers are over the insulating layer.