Class B FET amplifier circuit

• US RE31,749 E
• Filed: 07/11/1980
• Issued: 11/27/1984
• Est. Priority Date: 09/03/1975
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yamashiro, Osamu
• Primary Examiner(s): Anagnos, Larry N.
• Application Number:
  US06/168,777
• Time in Patent Office: 1,600 Days
• Field of Search: 307/451, 307/270, 307/260-261, 330/263, 330/264, 330/265, 330/267, 330/268, 330/277, 331/116 R, 331/116 FE
• US Class Current: 330/264
• CPC Class Codes: G04F 5/06 using piezoelectric resonators
• CPC Class Codes: H03F 3/3028 with symmetrical driving of the end stage
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

A complementary inverter amplifier circuit comprising a complementary inverter including a p-channel MIS FET connected to a first source potential, an n-channel MIS FET connected to a second source potential, the gate of the two FETs being applied with a common linear input, respective load resistors connected to the drains of the complementary FETs, an output being derived from the interconnection point of the load resistors or from the drains of the FETs, and a bias resistor connected between the gate and the drain of each of the complementary FETs, the input being supplied to the gates of the FETs through respective capacitors. The p-channel FET and n-channel FET are individually biased so that the circuit may serve as a class B push pull amplifier of low power consumption.

Claims

1. An FET circuit comprising an amplifier stage and a waveform shaping stage;

said amplifier stage including a first p-channel FET and a first n-channel FET, means for biasing the gate of each of said FETs at a dc level nearly equal to its drain potential.[.;

(.]..Iadd., .Iaddend.means for setting the potential differential between the source and the drain of each of said .[.FETS.]. .Iadd.FETs .Iaddend.at a voltage nearly equal to its threshold voltage.[.;

).]..Iadd., said potential differential setting means being coupled between the drains of said FETs, .Iaddend.and means for supplying a linear input signal to said gates through respective capacitors; and

said waveform shaping stage comprising means for converting a linear signal into a digital signal including a second p-channel FET having a gate coupled to the drain of said first p-channel FET, and a second n-channel FET having a gate coupled to the drain of said first n-channel FET .Iadd.and a drain coupled to the drain of said second p-channel FET, and output means coupled to the drains of the second p-channel and n-channel FETs for deriving the digital signal.Iaddend..

2. An amplifier circuit comprising a complementary inverter including a first FET of a first conductivity type connected to a first source potential, a second FET of a second conductivity type connected to a second source potential, and an input terminal connected to the gates of said first and second FETs, the circuit comprising:

a series connection of first and second load resistors connected between said first and second FETs;

a respective bias resistor connected between the gate and the drain of each of said first and second FETs;

a respective capacitor connected between the input terminal and the gate of each of said FETs; and

output means connected to the drains of said FETs.

3. The amplifier circuit according to claim 2, in which said output means comprises a terminal connected to the interconnection point of said load resistors.

4. The amplifier circuit according to claim 2, in which said output means comprises a pair of terminals connected to the drains of said first and second FETs, respectively. .[.

5. An amplifier circuit comprising, in combination, first and second operating voltage terminals of different potential level;

first and second field effect transistors (FET) of complementary conductivity type, each having a source, a gate and a drain, the sources of said complementary FETs being connected to said first and second operating voltage terminals respectively, the gates of said complementary FETs being ac-coupled to an input terminal; and

a resistor connected between the drains of said complementary FETs, the connection between said resistor and said complementary FETs serving as an output terminal..]. .[.6. The amplifier circuit according to claim 5, further comprising a biasing resistor connected between the gate and the drain of at least one of said first and second FETs, the bias potential between the gate and the source of said FETs being determined at a

6. potential nearly equal to its threshold voltage..]. 7. .[.The.]. .Iadd.An .Iaddend.amplifier circuit .[.according to claim 5, further comprising.]. .Iadd.comprising, in combination, first and second operating voltage terminals of different potential level;

first and second FETs of complementary conductivity type, each having a source, a gate and a drain, the sources of said complementary FETs being connected to said first and second operating voltage terminal respectively, the gates of said complementary FETs being ac-coupled to an input terminal;

a resistor connected between the drains of said complementary FETs, the connection between said resistor and at least one of said complementary FETs serving as an output terminal; and

bias means for applying the gates of said complementary FETs with bias voltages which have different potentials, wherein said bias means includes .Iaddend.a first and a second biasing .[.resistors.]. .Iadd.resistor .Iaddend.connected between the gates and the drains of said first and second FETs respectively, and an ac coupling capacitor connected between the gate of said first FET and said input terminal, the input terminal being connected directly to the gate of said second FET. .[.8. A complementary push-pull amplifier comprising;

a p-channel FET having a source coupled to a positive power source terminal, a gate and a drain;

an n-channel FET having a source coupled to a negative power source terminal, a gate and a drain;

resistive means coupled between said drains of said FETs and;

means for applying an a.c. input signal to said gates of said FETs to operate said FETs in a push-pull mode..]. .[.9. The amplifier as defined in claim 8 further including means for applying to the gate of one of said FETs a bias voltage substantially equal to its drain d.c. potential..].

8. d.c. blocking capacitor coupled between said gates of said FETs. 11. A complementary push-pull .Iadd.amplifier .Iaddend.comprising a p-channel FET, an n-channel FET, resistive load means connected .[.to at least one of.]. .Iadd.between the drains of .Iaddend.said FETs, a resistive bias means coupled between the gate and drain of .[.said.]. one .[.FET.]. .Iadd.of said FETs .Iaddend.for applying a bias voltage substantially equal to the drain d.c. potential of said FET to said gate thereof, .Iadd.another bias means for applying the gate of the other FET with a bias voltage which has a potential different from the potential at the gate of said one FET, .Iaddend.means for connecting said FETs and said resistive load means so that said resistive load means and the conduction paths between the sources and the drains of the respective FETs are connected in series and, means for applying an a.c. input signal to the gates of said FETs, the resistance of said load means being higher than the on-resistance of said one FET and the potential differential between the source and gate of said one FET approaching its threshold voltage .Iadd.and, output means coupled to the drain of at least one of said FETs

12. n-channel FETs serving as said output means. .Iaddend. .Iadd.18. The amplifier as defined in claim 17, in which said another resistive means comprises two resistive means connected in series, the node between the two resistive means serving as another output means. .Iaddend. .Iadd.19. An amplifier comprising

a first series circuit of first p-channel and n-channel FETs connected between a pair of power source terminals, and

a second series circuit of second p-channel and n-channel FETs connected between said power source terminals,

said first series circuit including resistive connection means for connecting the drain of said first p-channel FET to the drain of said first n-channel FET and bias means for applying to the gate of each of said first p-channel and n-channel FETs from the drain thereof a bias voltage substantially equal to the drain d.c. potential, and input means coupled to the gates of said first p-channel and n-channel FETs for applying an input signal to said gates, and

said second series circuit including first connecting means for connecting the drains of said second p-channel and n-channel FETs in common, and second connecting means for connecting the gates of said second p-channel and n-channel FETs to the drains of said first p-channel and n-channel FETs respectively, thereby causing respective bias points of said second p-channel and n-channel FETs to be substantially equal to those of said first p-channel and n-channel FETs, respectively, the drains of the second p-channel and n-channel FETs serving as an output means. .Iaddend.

10. least one output from the node between the drains of both FETs..]. 13. The amplifier as defined in claim .[.12.]. .Iadd.22 in which a single capacitor is connected between the gates of .Iadd.said .Iaddend.both FETs, said a.c. input signal being directly applied to the gate of one of said FETs and being applied to the gate of the other by way of said single capacitor. .[.14. A complementary FET circuit comprising an amplifier stage and a succeeding state, each being comprised of complementary FETs, said amplifier stage including means for producing two output signals having d.c. potentials different from each other in response to an input signal, said succeeding stage having two input terminals for receiving

13. Iadd. . An amplifier circuit comprising:

a p-channel FET;

an n-channel FET, the conduction path between the source and the drain thereof being connected in series with the conduction path between the source and the drain of said p-channel FET between a pair of power source terminals;

means coupled between said drains of said both FETs for producing two output signals at said drains, the two output signals having different d.c. potentials, the difference between the d.c. potentials being determined by a voltage drop across said means;

first bias means coupled between said drain and said gate of said p-channel FET for causing the gate potential to respond to the drain d.c. potential thereof;

second bias means coupled between said drain and said gate of said n-channel FET for causing the gate potential to respond to the drain d.c. potential thereof; and

means for applying an input signal to both gates of said FETs. .Iaddend. .Iadd.21. A complementary inverter amplifier circuit comprising, in combination,

a first and a second inverting amplifier device of complementary types each having a common electrode, an input electrode and an output electrode and operating in push-pull mode;

a power source, the both ends of which are coupled between said common electrodes for applying an operating energy to said first and second inverting amplifier devices;

an input terminal for applying an input signal to said input electrodes of said first and second inverting amplifier devices in common-mode;

bias means for applying said input electrodes of said first and second inverting amplifier devices with bias voltages which have different potentials;

an a.c. coupling capacitor coupled between said input electrodes of said first and second inverting amplifier devices;

a circuit device coupled between said output electrode of said first and second inverting amplifier devices for producing two output signals which have a phase being opposite to the phase of the common-mode signals at said input electrodes of said first and second inverting amplifier devices, and which have different d.c. potentials; and

a succeeding complementary inverter amplifier stage having two input terminals for receiving said two output signals and having an output terminal for deriving an output signal which has the same phase as said common-mode signals at said input electrodes of said first and second

14. inverting amplifier devices. .Iaddend. .Iadd.22. A complementary push-pull amplifier comprising a p-channel FET, an n-channel FET, resistive load means connected between the drains of said FETs, a resistive bias means coupled between the gate and drain of one of said FETs for applying a bias voltage substantially equal to the drain d.c. potential of said FET to said gate thereof, another resistive bias means coupled between the gate and the drain of the other FET for applying a bias voltage substantially equal to the drain d.c. potential of the other FET to the gate thereof, a d.c. blocking capacitor coupled between the gate of said FETs, means for connecting said FETs and said resistive load means so that said resistive load means and the conduction paths between the sources and the drains of the respective FETs are connected in series and, means for applying an a.c. input signal to the gates of said FETs, the resistance of said load means being higher than the on-resistance of said one FET and the potential differential between the source and gate of said one FET approaching its threshold voltage, and output deriving means wherein said load means is coupled between the drains of both FETs so as to act as a common load for said both FETs, said output deriving means deriving at least one output from the drains of both FETs. .Iaddend.

7. [.The.]. .Iadd.A complementary push-pull .Iaddend.amplifier .[.as defined claim 9 further including.]. .Iadd.comprising:

a p-channel FET having a source coupled to a positive power source terminal, a gate and a drain;

an n-channel FET having a source coupled to a negative power source terminal, a gate and a drain;

resistive means coupled between said drains of said FETs;

means for applying an a.c. input signal to said gates of said FETs to operate said FETs in a push-pull mode;

bias means for applying the gate of said FETs with bias voltages which have different potentials, said bias means including means for applying to the gate of one of said FETs a bias voltage substantially equal to its drain d.c. potential; and

.Iaddend.means for applying to the gate of the other FET a bias voltage substantially equal to its drain d.c. potential, and a

9. for deriving at least one output signal.Iaddend.. .[.12. The amplifier as defined in claim 11 comprising a d.c. blocking capacitor coupled between the gates of said FETs, resistive bias means coupled between the gate and drain of the other FET of applying a bias voltage substantially equal to the drain d.c. potential of the other FET to the gate thereof and, output deriving means wherein said load means is coupled between the drains of both FETs so as to act as a common load for said FETs, the resistance of said load means being higher than the on-resistance of the other FET and the potential differential between the source and gate of the other FET approaching its threshold voltage, said output deriving means deriving at

11. said two output signals..]. .[.15. The FET circuit as defined in claim 14, in which each of said stages comprises a p-channel FET and an n-channel FET, the respective potential differential between the source and the drain of each FET in said amplifier stage is supplied between the source and the gate of the corresponding FET in said succeeding stage, respectively, and said respective potential differential is substantially equal to the threshold voltage of that FET..]. .Iadd.16. A complementary push-pull amplifier comprising:

a first p-channel and a first n-channel FET;

a pair of bias resistive means each connected between the gate and the drain of said each FET;

another resistive means connected between the drains of said first p-channel and n-channel FETs;

capacitive means connected between the gates of said first p-channel and n-channel FETs;

input means coupled to the gates of said first p-channel and n-channel FETs for applying an input signal to said gates; and

output means coupled to said drains of said first p-channel and n-channel FETs for deriving at least one output signal. .Iaddend. .Iadd.17. The amplifier as defined in claim 16 further comprising a succeeding amplifier including a second p-channel and a second n-channel FET, the drains of which are connected to each other, the gates of the second p-channel and n-channel FETs being connected to said drains of said first p-channel and n-channel FETs, respectively, the drains of the second p-channel and