Directly bonded SIMM module

  • US RE36,325 E
  • Filed: 09/26/1995
  • Issued: 10/05/1999
  • Est. Priority Date: 09/30/1988
  • Status: Expired due to Term
First Claim
Patent Images

1. A memory array in which a plurality of memory circuit devices are arranged in a manner such that memory information is obtained by addressing bits of information from a selected number of the memory devices in the array in a format, and the format of bits forms a byte of memory data such that each byte includes bits from each memory device in the selected number of the circuit devices, and wherein the bits are addressed as rows and columns of information in a matrix on each memory device, characterized by:

  • (a) a support structure which includes a single polymeric sheet, the polymeric sheet having a plurality of die receiving portions thereon, having tape automated bond (TAB) leads thereon and having a first set of electrical circuit traces on one side of the polymeric sheet, the tape automated bond pads being in electrical communication with the circuit traces;

    (b) a plurality of integrated circuitry memory devices, each device consisting of circuit elements deposited on a substrate and having conductive bumps deposited thereon, the integrated circuit devices being located within separate ones of the receiving portions of the single polymeric sheet, and connected to the polymeric sheet by being attached to the tape automated bond pads at the conductive bumps, and each of the integrated circuit devices being connected to the TAB leads on the polymeric sheet within its respective die receiving portion;

    (c) a second set of circuit traces on a plane which is separate from said one side of the polymeric sheet, the second set of circuit traces being in electrical communication with the first set of electrical circuit traces;

    (d) circuit terminals in electrical communication with the circuit traces, the circuit terminals configured in a pattern which conforms to a predetermined external circuit connection and memory address protocol; and

    (e) means to mechanically stabilize the memory array so that the polymeric sheet, the memory devices and the circuit terminals are maintained in electrical communication during normal service.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×