Time delayed digital video system using concurrent recording and playback

  • US RE36,801 E
  • Filed: 04/18/1996
  • Issued: 08/01/2000
  • Est. Priority Date: 10/29/1992
  • Status: Expired due to Term
First Claim
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1. In combination,means for generating a substantially continuous sequence of .[.a.]. digital .[.television.]. input signal values .Iadd.representing an incoming audio or video program signal.Iaddend.,a source of control commands,a .[.television.]. .Iadd.program .Iaddend.signal utilization device, anda variable delay circular storage buffer .Iadd.for storing those of said digital input signal values which were received during the immediately preceding time intervals of predetermined duration, said circular storage buffer .Iaddend.having an input port connected to receive said digital .[.television.]. input signal values and an output port connected to supply a delayed replica of said input signal values to said utilization device following a variable delay interval, the duration of said interval being selectable in response to said control commands, said circular storage buffer comprising, in combination:

  • an addressable digital memory,a programmed processor,memory access means for continuously writing said sequence of digital .[.television.]. input signal values into said addressable digital memory.[.,.]. at a sequence of .Iadd.continually advancing .Iaddend.writing addresses established by said processor .Iadd.to write over the oldest of said input signal values recorded in said digital memory as said sequence of writing addresses are advanced so that said digital input signal values received during said immediately preceding time interval of predetermined duration are stored in said addressable digital memory, .Iaddend.and for concurrently reproducing and supplying to said output port an output sequence of previously written ones of signal values read from said addressable digital memory at a sequence of different reading addresses established by said processor, andmeans for supplying said output sequence to said output port,wherein said programmed processor includes means responsive to said control commands for varying the relative locations of said reading and writing addresses to selectively alter said variable delay interval.

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