Partial response trellis decoder for high definition television (HDTV) system

• US RE36,980 E
• Filed: 04/01/1998
• Issued: 12/05/2000
• Est. Priority Date: 04/12/1994
• Status: Expired due to Term

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Kwak, Heung S., Kim, Dae J., Nam, Ho J.
• Primary Examiner(s): Kostak, Victor R.
• Application Number:
  US09/053,131
• Time in Patent Office: 979 Days
• Field of Search: 375/265, 375/346, 455/295, 455/296, 455/303, 348/21, 348/608, 348/611, 348/614, 348/461, 348/466, 348/470
• US Class Current: 348/608
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0065 Serial concatenated codes
• CPC Class Codes: H04L 25/497 by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343

Abstract

A partial response Trellis decoder that performs Trellis coded modulation in a high definition television (HDTV) having a specific and detailed configuration and includes a distance mapper for calculating first, second, third and fourth Euclidean distances between the input signal and a reference value; a Viterbi decoder for Viterbi decoding the first, second, third and fourth Euclidean distances calculated by the distance mapper; a first delay for delaying and outputting the Yiterbi decoded data for each Euclidean distance; a ruler selector for selecting a ruler type signal based on the signals output by the first delay; and a slicer for slicing the selected ruler type signal and the input signal.

Claims

1. A partial response Trellis decoder for a high definition television (HDTV), said partial response Trellis decoder receiving an input signal from which NTSC interference has been removed and said partial response Trellis decoder comprises:

a distance mapper for calculating first, second, third and fourth Euclidean distances between said input signal and a reference value;

a Viterbi decoder for Viterbi decoding said first, second, third and fourth Euclidean distances calculated by said distance mapper;

a first delay for delaying and outputting the Viterbi decoded data for each Euclidean distance;

a ruler selector for selecting a ruler type signal based on the signals output by said first delay; and

a slicer for slicing said selected ruler type signal and said input signal.

2. The partial response Trellis decoder for a HDTV as claimed in claim 1, further comprising a second delay for delaying said input signal for a constant time in order to synchronize the input of said input signal to said slicer with the input of said ruler type signal to said slicer.

3. The partial response Trellis decoder for a HDTV as claimed in claim 1, wherein said distance mapper obtains a first Euclidean distance, by using the point closest among (0, 8, -8) to said input signal as said reference value, a second Euclidean distance is calculated by using the point closest among (2, 10, -6, -14) to said input signal as said reference value, a third Euclidean distance is calculated by using the closest point among (4, 12, -4, -12) to said input signal as said reference value, and a fourth Euclidean distance is calculated by using the point closest among (6, 14, -2, -10) to said input signal as said reference value.

4. The partial response Trellis decoder for a HDTV as claimed in claim 1, wherein said first delay delays the data output by said Viterbi decoder through three delays and outputs a current state and a next state to said ruler selector.

5. The partial response Trellis decoder for a HDTV as claimed in claim 4, wherein said first delay includes:

a single delay for delaying the data output by said Viterbi decoder by 12 symbols and for outputting said single delayed signal to said ruler selector;

a second delay for delaying the data output by said single delay by 12 symbols and for outputting said second delayed signal to said ruler selector; and

a third delay for delaying the data output by said second delay by 12 symbols and for outputting said third delayed signal to said ruler selector.

6. The partial response Trellis decoder for a HDTV as claimed in claim 1, wherein said ruler selector selects a first, second, third, fourth, fifth, sixth or seventh ruler type I, II, III, IV, V, VI or VII based on the signals output by said first delay.

7. The partial response Trellis decoder for a HDTV as claimed in claim 4, wherein said ruler selector selects:

a fourth ruler type IV if the current state signal is (000) and the next state signal is (000);

a second ruler type II if the current state signal is (000) and the next state signal is (100);

a fifth ruler type V if the current state signal is (100) and the next state signal is (010);

a third ruler type III if the current state signal is (100) and the next state signal is (110);

a third ruler type III if the current state signal is (010) and the next state signal is (001);

a fifth ruler type V if the current state signal is (010) and the next state signal is (101);

a fourth ruler type IV if the current state signal is (110) and the next state signal is (011);

a sixth ruler type VI if the current state signal is (110) and the next state signal is (111);

a sixth ruler type VI if the current state signal is (001) and the next state signal is (000);

a fourth ruler type IV if the current state signal is (001) and the next state signal is (100);

a third ruler type III if the current state signal is (101) and the next state signal is (010);

a first ruler type I if the current state signal is (101) and the next state signal is (110);

a fifth ruler type V if the current state signal is (011) and the next state signal is (001);

a seventh ruler type VII if the current state signal is (011) and the next state signal is (101);

a second ruler type II if the current state signal is (111) and the next state signal is (011); and

a fourth ruler type IV if the current state signal is (111) and the next state signal is (111).

8. The partial response Trellis decoder for a HDTV as claimed in claim 1, wherein:

if said selected ruler type is ruler type I, said slicer outputs `1` if said input signal is close to -14 or 2 and `0` if said input signal is close to -6;

if said selected ruler type is ruler type II, the slicer outputs `1` if said input signal is close to -12 or 4 and `0` if said input signal is close to -4;

if said selected ruler type is ruler type III, the slicer outputs `1` if said input signal is close to -10 or 6 and `0` if said input signal is close to -2;

if said selected ruler type is ruler type IV, the slicer outputs `1` if the input signal is close to -8 or 8 and `0` if the input signal is close to 0;

if said selected ruler type is ruler type V, the slicer outputs `1` if the input signal is close to -6 or 10 and `0` if the input signal is close to 2;

if said selected ruler type is ruler type VI, the slicer outputs `1` if the input signal is close to -4 or 12 and `0` if the input signal is close to 4; and

if the selected ruler type is ruler type VII, the slicer outputs `1` if the input signal is close to 14 or -2 and `0` if the input signal is close to 6.

9. A partial response Trellis decoder for a high definition television (HDTV), said partial response Trellis decoder receiving an input signal from which NTSC interference has been removed and said partial Trellis decoder comprises:

a distance mapper for calculating first, second, third and fourth Euclidean distances between said input signal and a reference value;

a Viterbi decoder for Viterbi decoding the first, second, third and fourth Euclidean distances calculated by said distance mapper;

a first delay means for delaying and outputting the Viterbi decoded data for each Euclidean distance;

a ruler selector for selecting a ruler type signal based on the signals output by said first delay means;

a hard decider for slicing and hard deciding said input signal; and

a multiplexer for selecting and outputting one of the signals output by said hard decider.

10. The partial response Trellis decoder for a HDTV as claimed in claim 9, further comprising second delay means for delaying the signal output from said hard decider for synchronizing the outputs of said hard decider, with outputs of said selected ruler type signal, the synchronized output of the hard decider and said ruler type signal being input to said multiplexer.

11. The partial response Trellis decoder for a HDTV as claimed in claim 9, wherein said distance mapper obtains a first Euclidean distance, by using the point closest among (0, 8, -8) to said input signal as said reference value, a second Euclidean distance is calculated by using the point closest among (2, 10, -6, -14) to said input signal as said reference value, a third Euclidean distance is calculated by using the point closest among (4, 12, -4, -12) to said input signal as said reference value, and a fourth Euclidean distance is calculated by using the point closest among (6, 14, -2, -10) to said input signal as said reference value.

12. The partial response Trellis decoder for a HDTV as claimed in claim 9, wherein said first delay means delays the data output by said Viterbi decoder through three delays and outputs current state signal and a next state to said ruler selector.

13. The partial response Trellis decoder for a HDTV as claimed in claim 12, wherein said first delay means includes:

a single delay for delaying the data output by said Viterbi decoder by 12 symbols and for outputting said single delayed signal to said ruler selector;

a second delay for delaying the data output by said single delay by 12 symbols and for outputting said second delayed signal to said ruler selector; and

a third delay for delaying the data output by said second delay by 12 symbols and for outputting said third delayed signal to said ruler selector.

14. The partial response Trellis decoder for a HDTV as claimed in claim 9, wherein said ruler selector selects a first, second, third, fourth, fifth, sixth or seventh ruler type I, II, III, IV, V, VI or VII based on the signals output by said first delay means.

15. The partial response Trellis decoder for a HDTV as claimed in claim 12, wherein said ruler selector selects:

a fourth ruler type IV if the current state signal is (000) and the next state signal is (000);

a second ruler type II if the current state signal is (000) and the next state signal is (100);

a fifth ruler type V if the current state signal is (100) and the next state signal is (010);

a third ruler type III if the current state signal is (100) and the next state signal is (110);

a third ruler type III if the current state signal is (010) and the next state signal is (001);

a fifth ruler type V if the current state signal is (010) and the next state signal is (101);

a fourth ruler type IV if the current state signal is (110) and the next state signal is (011);

a sixth ruler type VI if the current state signal is (110) and the next state signal is (111);

a sixth ruler type VI if the current state signal is (001) and the next state signal is (000);

a fourth ruler type IV if the current state signal is (001) and the next state signal is (100);

a third ruler type III if the current state signal is (101) and the next state signal is (010);

a first ruler type I if the current state signal is (101) and the next state signal is (110);

a fifth ruler type V if the current state signal is (011) and the next state signal is (001);

a seventh ruler type VII if the current state signal is (011) and the next state signal is (101);

a second ruler type II if the current state signal is (111) and the next state signal is (011); and

a fourth ruler type IV if the current state signal is (111) and the next state signal is (111).

16. The partial response Trellis decoder for a HDTV as claimed in claim 9, wherein:

if said selected ruler type is ruler type I, said hard decider outputs `1` if said input signal is close to -14 or 2 and `0` if said input signal is close to -6;

if said selected ruler type is ruler type II, the hard decider outputs `1` if said signal is close to -12 or 4 and `0` if said input signal is close to -4;

if said selected ruler type is ruler type III, the hard decider outputs `1` if said input signal is close to -10 or 6 and `0` if said input signal is close to -2;

if said selected ruler type is ruler type IV, the hard decider outputs `1` if the input signal is close to -8 or 8 and `0` if the input signal is close to 0;

if said selected ruler type is ruler type V, the hard decider outputs `1` if the input signal is close to -6 or 10 and `0` if the input signal is close to 2;

if said selected ruler type is ruler type VI, the hard decider outputs `1` if the input signal is close to -4 or 12 and `0` if the input signal is close to 4; and

if the selected ruler is ruler type VII, the hard decider outputs `1` if the input signal is close to 14 or -2 and `0` if the input signal is close to 6.

17. A partial response Trellis decoder for a high definition television (HDTV), said partial response Trellis decoder receiving an input signal from which NTSC interferences have been removed and said partial Trellis decoder comprises:

a distance mapper for calculating first, second, third and fourth Euclidean distances between said input signal and a reference value;

a hard decider for hard deciding said input signal and for outputting the hard decision value; and

a Viterbi decoder for Viterbi decoding the data output by said distance mapper and said hard decider.

18. The partial response Trellis decoder for a HDTV as claimed in claim 17, wherein said Viterbi decoder comprises:

a matrix calculator for obtaining the difference between the Euclidean distances output by said distance mapper and branches of the respective states and for calculating a survival path and an accumulative matrix value by adding the difference value with an accumulative previous distance value;

an optional path calculator for obtaining the optimal path within a view area from the accumulative matrix value output by said matrix calculator;

a path history calculator for directly outputting the upper one bit value of the output by said hard decider, the survival path output by the matrix calculator, and the optimal path output by the optimal path calculator, and for outputting a signal for selecting the lower one bit; and

a look-up table for outputting the lower one bit depending on the selection signal output by the path history calculator.

19. The partial response Trellis decoder for a HDTV as claimed in claim 17, wherein said distance mapper obtains a first Euclidean distance, by using the point closest among (0, 8, -8) to said input signal as said reference value, a second Euclidean distance is calculated by using the point closest among (2, 10, -6, -14) to said input signal as said reference value, a third Euclidean distance is calculated by using the point closest among (4, 12, -4, -12) to said input signal as said reference value, and a fourth Euclidean distance is calculated by using the point closest among (6, 14, -2, -10) to said input signal as said reference value.

20. The partial response Trellis decoder for a HDTV as claimed in claim 17, wherein:

if a selected ruler type is ruler type I, said hard decider outputs `1` if said input signal is close to -14 or 2 and `0` if said input signal is close to -6;

if said selected ruler type is ruler type II, the hard decider outputs `1` if said input signal is close to -12 or 4 and `0` if said input signal is close to -4;

if said selected ruler type is ruler type III, the hard decider outputs `1` if said input signal is close to -10 or 6 and `0` if said input signal is close to -2;

if said selected ruler type is ruler type IV, the hard decider outputs `1` if the input signal is close to -8 or 8 and `0` if the input signal is close to 0;

if said selected ruler type is ruler type V, the hard decider outputs `1` if the input signal is close to -6 or 10 and `0` if the input signal is close to 2;

if said selected ruler type is ruler type VI, the hard decider outputs `1` if the input signal is close to -4 or 12 and `0` if the input signal is close to 4; and

if the selected ruler type is ruler type VII, the hard decider outputs `1` if the input signal is close to 14 or -2 and `0` if the input signal is close to 6. .Iadd.

21. A digital television system comprising:

a decoder receiving an input signal and comprising a first Trellis decoder unit and a second Trellis decoder unit;

a switch coupled to the first and second Trellis decoder units, the switch selecting the first Trellis decoder unit when the input signal contains an NTSC signal and the switch selecting the second Trellis decoder unit when the input signal does not contain an NTSC signal;

a filter coupled to the first Trellis decoder unit, the filter removing the NTSC signal from the input signal and outputting a filtered signal to the first Trellis decoder unit;

the first Trellis decoder unit comprising;

a distance mapper receiving the filtered signal from the filter;

a Viterbi decoder coupled to the distance mapper;

a first delay unit coupled to the Viterbi decoder;

a ruler selector coupled to the first delay unit; and

a slicer coupled to the ruler selector; and

the second Trellis decoder unit comprising a third decoder, the third decoder including a second delay unit and an adder coupled to the second delay unit. .Iaddend..Iadd.22. The digital television system according to claim 21, wherein the filter comprises;

a third delay unit receiving an NTSC included signal and producing a delayed NTSC included signal; and

a subtractor subtracting the NTSC included signal from the delayed NTSC

22. included signal. .Iaddend..Iadd.23. The digital television system according to claim 21, wherein the second Trellis decoder unit includes a four state optimal Trellis decoder. .Iaddend..Iadd.24. A digital television system comprising:

an encoder unit comprising;

a first encoder receiving a first input signal including;

an adder receiving the first input signal and outputting a first encoded signal; and

a first delay unit coupled to the adder;

a second encoder receiving a second input signal and outputting second and third encoded signals;

a mapper receiving the first, second, and third encoded signals from the first and second encoders, respectively;

a decoder unit including a first Trellis decoder unit and a second Trellis decoder unit, the decoder unit comprising;

a switch coupled to the first and second Trellis decoder units, the switch selecting the first Trellis decoder unit when the input signal contains an NTSC signal and the switch selecting the second Trellis decoder unit when the input signal does not contain an NTSC signal;

a filter coupled to the first Trellis decoder unit, the filter removing the NTSC signal from the input signal and outputting a filtered signal to the first Trellis decoder unit;

the first Trellis decoder unit comprising;

a distance mapper receiving the filtered signal from the filter;

a Viterbi decoder coupled to the distance mapper;

a second delay unit coupled to the Viterbi decoder;

a ruler selector coupled to the second delay unit; and

a slicer coupled to the ruler selector; and

the second Trellis decoder unit comprising a third decoder, the third decoder including a third delay unit and a subtractor coupled to the third delay unit. .Iaddend..Iadd.25. The digital television system according to claim 24, wherein the filter comprises;

a fourth delay unit receiving an NTSC included signal and producing a delayed NTSC included signal; and

a subtractor adding the NTSC included signal to the delayed NTSC included

26. Iaddend..Iadd.36. The digital television system according to claim 35, wherein the Trellis decoder includes a four state optimal Trellis decoder. .Iaddend..Iadd.37. A digital television signal comprising:

an encoder unit comprising;

a first encoder receiving a first input signal including;

an adder receiving the first input signal and outputting a first encoded signal; and

a first delay unit coupled to the adder;

a second encoder receiving a second input signal and outputting second and third encoded signals;

a mapper receiving the first, second, and third encoded signals from the first and second encoders, respectively;

a Trellis decoder receiving an encoded signal from the encoder unit comprising;

a distance mapper receiving the encoded signal;

a Viterbi decoder coupled to the distance mapper;

a slicer coupled to the Viterbi decoder; and

a second decoder coupled to the Trellis decoder, the second decoder including a second delay unit and an adder coupled to the second delay

27. unit. .Iaddend..Iadd.38. The digital television system according to claim 37, wherein the Trellis decoder includes a four state optimal Trellis decoder. .Iaddend..Iadd.39. The digital television system according to claim 37, wherein the second encoder includes:

a third delay unit receiving the second input signal;

a fourth delay unit coupled to the third delay unit;

a first exclusive OR gate coupled to the third and fourth delay units; and

a second exclusive OR gate coupled to the fourth delay unit. .Iaddend..Iadd.40. A digital television system having an encoder unit, the encoder comprising;

a first encoder receiving a first input signal including;

an adder receiving the first input signal and outputting an first encoded signal; and

a delay unit coupled to the adder;

a second encoder receiving a second input signal and outputting second and third encoded signals; and

a mapper receiving the first, second, and third encoded signals from the

28. first and second encoders, respectively. .Iaddend..Iadd.41. The digital television system according to claim 40, wherein the second encoder includes:

a second delay unit receiving the second input signal;

a third delay unit coupled to the second delay unit;

a first exclusive OR gate coupled to the second and third delay units; and

a second exclusive OR gate coupled to the third delay unit. .Iaddend..Iadd.42. A method for decoding an input signal for a digital television system, the method comprising the steps of;

Trellis decoding the input signal, the decoding step comprising the steps of;

receiving the input signal and mapping the input signal to produce a mapped signal for determining a distance error in the input signal;

slicing the input signal; and

Viterbi decoding the mapped signal and the sliced input signal and outputting a Viterbi decoded signal;

delaying the Viterbi decoded signal; and

adding the Viterbi decoded signal and the delayed Viterbi decoded signal. .Iaddend..Iadd.43. A method for encoding a signal for a digital television system, the method comprising the steps of;

receiving a first input signal and adding the first input signal to a feedback signal to produce an added signal, the added signal including a first encoded signal; and

delaying the added signal to produce the feedback signal, the feedback signal including the added signal;

receiving a second input signal and outputting second and third encoded signals; and

23. signal. .Iaddend..Iadd.26. The digital television system according to claim 24, wherein the second Trellis decoder unit includes a four state optimal Trellis decoder. .Iaddend..Iadd.27. The digital television system according to claim 24, wherein the second encoder includes:

a fourth delay unit receiving the second input signal;

a fifth delay unit coupled to the fourth delay unit;

a first exclusive OR gate coupled to the fourth and fifth delay units; and

a second exclusive OR gate coupled to the fifth delay unit.

24. Iaddend..Iadd. 8. A digital television system comprising:

a decoder receiving an input signal and comprising a first Trellis decoder unit and a second Trellis decoder unit;

a switch coupled to the first and second Trellis decoder units, the switch selecting the first Trellis decoder unit when the input signal contains an NTSC signal and the switch selecting the second Trellis decoder unit when the input signal does not contain an NTSC signal;

a filter coupled to the first Trellis decoder unit, the filter removing the NTSC signal from the input signal and outputting a filtered signal to the first Trellis decoder unit;

the first Trellis decoder unit comprising;

a distance mapper receiving the filtered signal from the filter;

a Viterbi decoder coupled to the distance mapper;

a hard decider coupled to the Viterbi decoder; and

the second Trellis decoder unit comprising a third decoder, the third decoder including a delay unit and an adder coupled to the delayed unit. .Iaddend..Iadd.29. The digital television system according to claim 28, wherein the filter comprises;

a second delay unit receiving an NTSC included signal and producing a delayed NTSC included signal; and

an adder adding the NTSC included signal to the delayed NTSC included signal. .Iaddend..Iadd.30. The digital television system according to claim 28, wherein the second Trellis decoder unit includes a four state

29. mapping the first, second, and third encoded signals. .Iaddend..Iadd.44. A method for operating a digital television system, the method comprising the steps of:

receiving a first input signal and adding the first input signal to a feedback signal to produce an added signal, the added signal including a first encoded signal; and

delaying the added signal to produce the feedback signal, the feedback signal including the added signal;

receiving a second input signal and outputting second and third encoded signals;

mapping the first, second, and third encoded signals and producing a transmission signal;

Trellis decoding the transmission signal, the decoding step comprising the steps of;

receiving the transmission signal and mapping the transmission signal to produce a mapped signal for determining a distance error in the transmission signal;

slicing the transmission signal; and

Viterbi decoding the mapped signal and the sliced transmission signal and outputting a Viterbi decoded signal;

delaying the Viterbi decoded signal; and

adding the Viterbi decoded signal and the delayed Viterbi decoded signal.

30. Iaddend..Iadd.45. A digital television system comprising:

a randomizer receiving an input signal;

an R-S encoder coupled to the randomizer;

a data interleaver coupled to the R-S encoder;

a Trellis encoder coupled to the data interleaver;

a multiplexer coupled to the Trellis encoder;

a pilot inserter coupled to the multiplexer;

a VSB modulator coupled to the pilot inserter; and

an RF up-converter coupled to the VSB modulator and outputting a transmission signal,

wherein the Trellis encoder includes;

a first encoder receiving a first input signal including;

an adder receiving the first input signal and outputting a first encoded signal; and

a delay unit coupled to the adder;

a second encoder receiving a second input signal and outputting second and third encoded signals; and

a mapper receiving the first, second, and third encoded signals from the first and second encoders, respectively. .Iaddend..Iadd.46. A digital television system comprising;

a tuner receiving a transmission signal;

a filter and sync signal detector coupled to the tuner;

a sync and timing unit coupled to the filter and sync signal detector;

an equalizer coupled to the sync and timing unit;

a phase tracker coupled to the equalizer;

a decoder unit coupled to the phase tracker;

a data deinterleaver coupled to the Trellis decoder;

an R-S decoder coupled to the data deinterleaver; and

a derandomizer coupled to the R-S decoder;

wherein the decoder unit includes;

a Trellis decoder having;

a distance mapper;

a Viterbi decoder coupled to the distance mapper; and

a slicer coupled to the Viterbi decoder; and

a second decoder coupled to the Trellis decoder, the second decoder including a delay unit and an adder coupled to the delay unit.

31. Iaddend..Iadd.47. The digital television according to claim 46, further comprising an NTSC rejection filter coupled to the filter and sync signal

25. optimal Trellis decoder. .Iaddend..Iadd.31. A digital television system comprising:

an encoder unit comprising;

a first encoder receiving a first input signal including;

an adder receiving the first input signal and outputting a first encoded signal; and

a first delay unit coupled to the adder;

a second encoder receiving a second input signal and outputting second and third encoded signals;

a mapper receiving the first, second, and third encoded signals from the first and second encoders, respectively;

a decoder unit including a first Trellis decoder unit and a second Trellis decoder unit, the decoder unit comprising;

a switch coupled to the first and second Trellis decoder units, the switch selecting the first Trellis decoder unit when the input signal contains an NTSC signal and the switch selecting the second Trellis decoder unit when the input signal does not contain an NTSC signal;

a filter coupled to the first Trellis decoder unit, the filter removing the NTSC signal from the input signal and outputting a filtered signal to the first Trellis decoder unit;

the first Trellis decoder unit comprising;

a distance mapper receiving the filtered signal from the filter;

a Viterbi decoder coupled to the distance mapper;

a slicer coupled to the Viterbi decoder; and

the second Trellis decoder unit comprising a third decoder, the third decoder including a second delay unit and a subtractor coupled to the second delay unit. .Iaddend..Iadd.32. The digital television system according to claim 31, wherein the filter comprises;

a third delay unit receiving an NTSC included signal and producing a delayed NTSC included signal; and

a subtractor subtracting the NTSC included signal from the delayed NTSC included signal. .Iaddend..Iadd.33. The digital television system according to claim 31, wherein the second Trellis decoder unit includes a four state optimal Trellis decoder. .Iaddend..Iadd.34. The digital television system according to claim 31, wherein the second encoder includes;

a third delay unit receiving the second input signal;

a fourth delay unit coupled to the third delay unit;

a first exclusive OR gate coupled to the third and fourth delay units; and

a second exclusive OR gate coupled to the fourth delay unit. .Iaddend..Iadd.35. A digital television system comprising;

a Trellis decoder receiving an encoded signal comprising;

a distance mapper receiving the encoded signal;

a Viterbi decoder coupled to the distance mapper;

a slicer coupled to the Viterbi decoder; and

a second decoder coupled to the Trellis decoder, the second decoder including a delay unit and an adder coupled to the delay unit.

32. detector and the equalizer. .Iaddend..Iadd.48. A digital television system comprising:

a transmitter unit including;

a randomizer receiving an input signal;

an R-S encoder coupled to the randomizer;

a data interleaver coupled to the R-S encoder;

a Trellis encoder coupled to the data interleaver;

a multiplexer coupled to the Trellis encoder;

a pilot inserter coupled to the multiplexer;

a VSB modulator coupled to the pilot inserter; and

an RF up-converter coupled to the VSB modulator and outputting a transmission signal,

wherein the Trellis encoder includes;

a first encoder receiving a first input signal including;

an adder receiving the first input signal and outputting a first encoded signal; and

a delay unit coupled to the adder;

a second encoder receiving a second input signal and outputting second and third encoded signals; and

a mapper receiving the first, second, and third encoded signals from the first and second encoders, respectively,

a receiver unit comprising;

a tuner receiving a transmission signal;

a filter and sync signal detector coupled to the tuner;

a sync and timing unit coupled to the filter and sync signal detector;

an equalizer coupled to the sync and timing unit;

a phase tracker coupled to the equalizer;

a decoder unit coupled to the phase tracker;

a data deinterleaver coupled to the Trellis decoder;

an R-S decoder coupled to the data deinterleaver; and

a derandomizer coupled to the R-S decoder;

wherein the decoder unit includes;

a Trellis decoder having;

a distance mapper;

a Viterbi decoder coupled to the distance mapper; and

a slicer coupled to the Viterbi decoder; and

a second decoder coupled to the Trellis decoder, the second decoder including a delay unit and an adder coupled to the delay unit.

33. Iaddend..Iadd.49. The digital television system according to claim 48, further comprising an NTSC rejection filter coupled to the filter and sync signal detector and the equalizer. .Iaddend.