Run to run control process for controlling critical dimensions

CAFC
  • US RE39,518 E1
  • Filed: 07/18/2001
  • Issued: 03/13/2007
  • Est. Priority Date: 05/28/1997
  • Status: Expired due to Term
First Claim
Patent Images

1. A method of fabricating an integrated circuit comprising:

  • pattern, exposure, and develop a photoresist layer on a wafer in a photolithography process that forms a plurality of structures on the integrated circuit including a gate;

    measuring a DICD critical dimension of the gate following developing of the photoresist layer in a Develop Inspection Critical Dimensions (DICD) operation;

    etching the wafer including etching of the gate;

    measuring a FICD critical dimension of the gate following etching of the wafer in a Final Inspection Critical Dimensions (FICD) operation;

    feeding forward the DICD critical dimension to a process model;

    feeding back the FICD critical dimension to the process model; and

    controlling a photoresist deposit and etch process recipe parameter in the process model according to the DICD critical dimension and the FICD critical dimension of the gate to improve critical dimension uniformity.

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