Run to run control process for controlling critical dimensions

• US RE39,518 E1
• Filed: 07/18/2001
• Issued: 03/13/2007
• Est. Priority Date: 05/28/1997
• Status: Expired due to Term

• Current Assignee: Lone Star Silicon Innovations LLC (Tanit Ventures Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Toprac, Anthony John, Downey, Douglas John, Gupta, Subhash
• Primary Examiner(s): Coleman, W. David
• Application Number:
  US09/908,390
• Time in Patent Office: 2,064 Days
• Field of Search: 438/17, 438/16, 438/725, 438/780
• US Class Current: 438/17
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time of photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a manipulated variable in either a feedforward or a feedback control configuration to control critical dimension variation during semiconductor fabrication. By controlling critical dimensions through the adjustment of photoresist etch time, many advantages are achieved including a reduced lot-to-lot variation, an increased yield, and increased speed of the fabricated circuits. In one embodiment these advantages are achieved for polysilicon gate critical dimension control in microprocessor circuits. Polysilicon gate linewidth variability is reduced using a control method using either feedforward and feedback or feedback alone. In some embodiments, feedback control is implemented for controlling critical dimensions using photoresist each time as a manipulated variable. In an alternative embodiment, critical dimensions are controlled using RF power as a manipulated variable. A run-to-run control technique is used to drive the critical dimensions of integrated circuits to a set specification. In a run-to-run control technique a wafer test or measurement is made and a process control recipe is adjusted based on the result of the test or measurement on a run-by-run basis. The run-to-run control technique is applied to drive the critical dimensions of a polysilicon gate structure to a target specification. The run-to-run control technique is applied to drive the critical dimensions in an integrated circuit to a defined specification using photoresist etch time as a manipulated variable.

Claims

1. A method of fabricating an integrated circuit comprising:

pattern, exposure, and develop a photoresist layer on a wafer in a photolithography process that forms a plurality of structures on the integrated circuit including a gate;

measuring a DICD critical dimension of the gate following developing of the photoresist layer in a Develop Inspection Critical Dimensions (DICD) operation;

etching the wafer including etching of the gate;

measuring a FICD critical dimension of the gate following etching of the wafer in a Final Inspection Critical Dimensions (FICD) operation;

feeding forward the DICD critical dimension to a process model;

feeding back the FICD critical dimension to the process model; and

controlling a photoresist deposit and etch process recipe parameter in the process model according to the DICD critical dimension and the FICD critical dimension of the gate to improve critical dimension uniformity.

2. A method according to claim 1 wherein:

the gate is a polysilicon gate.

3. A method according to claim 1 further comprising:

initially underexposing the wafer to initially produce DICD and FICD critical dimensions that are larger than target critical dimension values.

4. A method according to claim 3 further comprising:

subsequent to initially underexposing the wafer, varying photoresist etch time to control driving of the FICD critical dimensions to the target critical dimension values.

5. A method according to claim 4 further comprising:

etching the wafer using an etch time set to a nominal photoresist etch time that is based on the initial, average, or moving average operating conditions of the fabrication method.

6. A method according to claim 1 wherein:

the DICD critical dimension measurement and the FICD critical dimension measurement are measured using a measurement technique selected from among scanning electron microscopy (SEM), mechanical measurement techniques, image shearing, and reflectance measurements.

7. A method according to claim 1 further comprising:

storing the DICD critical dimension measurement and the FICD critical dimension measurement in a database.

8. A method according to claim 1 further comprising:

filtering the DICD critical dimension measurement to supply a filtered feed-forward control of critical dimensions to the process model.

9. A method according to claim 1 further comprising:

filtering the FICD critical dimension measurement to supply a filtered feed-back control of critical dimensions to the process model.

10. A method according to claim 1 further comprising:

controlling the photoresist deposit and etch process recipe parameter in the process model according to a quadratic relationship between the DICD and the FICD critical dimensions and photoresist etch time.

11. A method according to claim 1 further comprising:

controlling the photoresist deposit and etch process recipe parameter in the process model according to a quadratic relationship between the DICD and the FICD critical dimensions and photoresist etch time as follows;

FICD=at²+bt+c,

which is solved using the quadratic formula, as follows;

$\begin{array}{cc}t=\frac{-b+\sqrt{b^2-4<br><br>a<br><br>\text{\hspace{1em}<br><br>}<br><br>c}}{2<br><br>a},& \text{\hspace{1em}<br><br>}\end{array}$

in which parameter c sets a current average operating point.

12. A method according to claim 1 further comprising

controlling the photoresist deposit and etch process recipe parameter in the process model according to a relationship between the difference of the DICD and the FICD critical dimensions and photoresist etch time as follows:

DICD−

FICD=CB+(2*ER*E*tan(k*ET+Θ

₀)),

in which CB is a chamber bias parameter, ER is etch rate, ET is etch time, and Θ

₀ is initial sidewall angle of the photoresist.

13. A method according to claim 1 further comprising:

performing a run-to-run control technique to drive the DICD and the FICD critical dimensions of a polysilicon gate structure to a target specification.

14. A method according to claim 1 further comprising:

exposing the photoresist at a selected radio frequency (RF) power; and

selecting the selected RF power as the selected photoresist deposit and etch process recipe parameter for controlling the DICD and FICD critical dimensions.

15. A method according to claim 1 wherein:

the photoresist deposit and etch process recipe parameter for controlling the DICD and the FICD critical dimensions is etch time.

16. A method according to claim 1 further comprising:

forming a polysilicon layer overlying a substrate;

depositing a photoresist layer on the polysilicon layer;

etching the deposited photoresist layer for a controlled photoresist etch time; and

etching the polysilicon layer subsequent to the step of etching the deposited photoresist layer.

17. A method according to claim 1 further comprising:

forming an anti-reflective coating beneath the photoresist layer using a Bottom Anti-Reflective Coating (BARC) etch step to reduce stray light photoresist exposure from reflections off a substrate.

18. A method of fabricating an integrated circuit comprising:

pattern, expose, and develop a photoresist layer on a plurality of wafers in a photolithography process that forms a plurality of structures on the integrated circuit including a gate;

measuring a DICD critical dimension of the gate in a pilot subset of the plurality of wafers following developing of the photoresist layer in a Develop Inspection Critical Dimensions (DICD) operation;

etching wafers of the plurality of wafers remaining after removal of the pilot subset, the etching including etching of the gate;

measuring a FICD critical dimension of the gate following etching of the plurality of wafers remaining after removal of the pilot subset in a Final Inspection Critical Dimensions (FICD) operation;

feeding forward the DICD critical dimension to a process model;

feeding back the FICD critical dimension to the process model; and

controlling a photoresist deposit and etch process recipe parameter in the process model according to the DICD critical dimension and the FICD critical dimension of the gate to improve critical dimension uniformity.

19. A method according to claim 18 further comprising:

dividing the plurality of wafers into two or more split subsets of wafers; and

processing the split subsets separately using different exposure levels to produce a respective two or more levels of DICD critical dimension measurements.

20. A method according to claim 18 wherein:

the photoresist deposit and etch process recipe parameter for controlling the DICD and the FICD critical dimensions is etch time.

21. A method of fabricating an integrated circuit device, comprising:

providing a wafer having a gate electrode material layer formed thereabove;

forming a patterned layer of photoresist above the gate electrode material layer;

performing a photoresist etching process on the patterned layer of photoresist;

etching the gate electrode material layer to define at least one gate electrode in said gate electrode material layer;

measuring a critical dimension of said at least one gate electrode; and

controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon said measured critical dimension and a target critical dimension for said at least one gate electrode.

22. The method of claim 21, wherein providing a wafer having a gate electrode material layer formed thereabove comprises providing a wafer having a gate electrode material layer comprised of polysilicon formed thereabove.

23. The method of claim 21, wherein forming a patterned layer of photoresist above the gate electrode material layer comprises forming a patterned layer of photoresist above the gate electrode material layer by performing at least an exposure process, a post-exposure bake process and a photoresist develop process.

24. The method of claim 21, wherein measuring a critical dimension of said at least one gate electrode comprises measuring a critical dimension of said at least one gate electrode by using at least one of scanning electron microscopy, image shearing, and reflective measurements.

25. The method of claim 21, further comprising storing said measured critical dimension in a database.

26. The method of claim 21, further comprising feeding back the measured critical dimension of the at least one gate electrode to a process model.

27. The method of claim 26, further comprising filtering the measured critical dimension prior to feeding back the measured critical dimension to the process model.

28. The method of claim 21, wherein controlling a duration of a photoresist etch process is based upon a comparison between said measured critical dimension and said target critical dimension for said at least one gate electrode.

29. The method of claim 21, wherein controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimension and a target critical dimension for said at least one gate electrode comprises controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a quadratic relationship between the measured critical dimension and the duration of the photoresist etch process.

30. The method of claim 21, further comprising measuring a critical dimension of a feature formed in said patterned layer of photoresist prior to performing said photoresist etching process.

31. The method of claim 30, wherein controlling a duration of a photoresist etching process comprises controlling a duration of said photoresist etching process based upon said measured critical dimension of said gate electrode, said measured critical dimension of said feature in said patterned layer of photoresist, and said target value for said gate electrode.

32. A method of fabricating an integrated circuit device, comprising:

providing a wafer having a gate electrode material layer comprised of polysilicon formed thereabove;

forming a patterned layer of photoresist above the gate electrode material layer;

performing a photoresist etching process on the patterned layer of photoresist;

etching the gate electrode material layer using the etched patterned layer of photoresist as a mask to define a plurality of gate electrodes comprised of polysilicon;

measuring a critical dimension of a plurality of said gate electrodes; and

controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of gate electrodes.

33. The method of claim 32, wherein forming a patterned layer of photoresist above the gate electrode material layer comprises forming a patterned layer of photoresist above the gate electrode material layer by performing at least an exposure process, a post-exposure bake process and a photoresist develop process.

34. The method of claim 32, wherein measuring a critical dimension of a plurality of gate electrodes comprises measuring a critical dimension of a plurality of gate electrodes by using at least one of scanning electron microscopy, image shearing, and reflective measurements.

35. The method of claim 32, further comprising storing said measured critical dimensions in a database.

36. The method of claim 32, further comprising feeding back the measured critical dimensions of the plurality of gate electrodes to a process model.

37. The method of claim 36, further comprising filtering the measured critical dimensions prior to feeding back the measured critical dimensions to the process model.

38. The method of claim 32, wherein controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension of said plurality of gate electrodes comprises controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a quadratic relationship between the measured critical dimensions and the duration of the photoresist etch process.

39. The method of claim 32, further comprising measuring a critical dimension of a feature formed in said patterned layer of photoresist prior to performing said photoresist etching process.

40. The method of claim 39, wherein controlling a duration of a photoresist etching process comprises controlling a duration of said photoresist etching process based upon said measured critical dimension of said gate electrode, said measured critical dimension of said feature in said patterned layer of photoresist, and said target value for said gate electrode.

41. A method of fabricating an integrated circuit device, comprising:

providing a wafer having a gate electrode material layer comprised of polysilicon formed thereabove;

forming a patterned layer of photoresist above the gate electrode material layer;

performing a photoresist etching process on the patterned layer of photoresist;

etching the gate electrode material layer using the etched patterned layer of photoresist as a mask to define a plurality of gate electrodes comprised of polysilicon;

measuring a critical dimension of a plurality of said gate electrodes;

feeding back the measured critical dimensions of the plurality of gate electrodes to a process model; and

controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of gate electrodes.

42. The method of claim 41, wherein forming a patterned layer of photoresist above the gate electrode material layer comprises forming a patterned layer of photoresist above the gate electrode material layer by performing at least an exposure process, a post-exposure bake process and a photoresist develop process.

43. The method of claim 41, wherein measuring a critical dimension of a plurality of gate electrodes comprises measuring a critical dimension of a plurality of gate electrodes by using at least one of scanning electron microscopy, image shearing, and reflective measurements.

44. The method of claim 41, further comprising filtering the measured critical dimensions prior to feeding back the measured critical dimensions to the process model.

45. The method of claim 41, wherein controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of gate electrodes comprises controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a quadratic relationship between the measured critical dimensions and the duration of the photoresist etch process.

46. The method of claim 41, further comprising storing said measured critical dimensions in a database.

47. The method of claim 41, further comprising measuring a critical dimension of a feature formed in said patterned layer of photoresist prior to performing said photoresist etching process.

48. The method of claim 47, wherein controlling a duration of a photoresist etching process comprises controlling a duration of said photoresist etching process based upon said measured critical dimension of said gate electrode, said measured critical dimension of said feature in said patterned layer of photoresist, and said target value for said gate electrode.

49. A method of fabricating an integrated circuit device, comprising:

providing a wafer having a gate electrode material layer formed thereabove;

forming a patterned layer of photoresist above the gate electrode material layer;

performing a photoresist etching process on the patterned layer of photoresist;

etching the gate electrode material layer to define at least one patterned feature in said gate electrode material layer;

measuring a critical dimension of said at least one patterned feature; and

controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon said measured critical dimension and a target critical dimension for said at least one patterned feature.

50. The method of claim 49, wherein providing a wafer having a gate electrode material layer formed thereabove comprises providing a wafer having a gate electrode material layer comprised of polysilicon formed thereabove.

51. The method of claim 49, wherein forming a patterned layer of photoresist above the gate electrode material layer comprises forming a patterned layer of photoresist above the gate electrode material layer by performing at least an exposure process, a post-exposure bake process and a photoresist develop process.

52. The method of claim 49, wherein measuring a critical dimension of said at least one patterned feature comprises measuring a critical dimension of said at least one patterned feature by using at least one of scanning electron microscopy, image shearing, and reflective measurements.

53. The method of claim 49, further comprising storing said measured critical dimension in a database.

54. The method of claim 49, further comprising feeding back the measured critical dimension of the at least one patterned feature to a process model.

55. The method of claim 54, further comprising filtering the measured critical dimension prior to feeding back the measured critical dimension to the process model.

56. The method of claim 49, wherein controlling at least parameter of a photoresist etch process is based upon a comparison between said measured critical dimension and said target critical dimension for said at least one patterned feature.

57. The method of claim 49, wherein controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimension and a target critical dimension for said at least one patterned feature comprises controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a quadratic relationship between the measured critical dimension and a duration of the photoresist etch process.

58. The method of claim 49, further comprising measuring a critical dimension of a feature formed in said patterned layer of photoresist prior to performing said photoresist etching process.

59. The method of claim 58, wherein controlling at least one parameter of a photoresist etching process comprises controlling at least one parameter of said photoresist etching process based upon said measured critical dimension of said at least one patterned feature, said measured critical dimension of said feature in said patterned layer of photoresist, and said target value for said at least one patterned feature.

60. The method of claim 49, wherein etching the gate electrode material layer to define at least one patterned feature in said gate electrode material layer comprises etching the gate electrode material layer to define at least one gate electrode in said gate electrode material layer.

61. The method of claim 60, wherein measuring a critical dimension of said at least one patterned feature comprises measuring a critical dimension of said at least one gate electrode.

62. The method of claim 49, wherein controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon said measured critical dimension and a target critical dimension for said at least one patterned feature comprises controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon said measured critical dimension and a target critical dimension for said at least one patterned feature.

63. A method of fabricating an integrated circuit device, comprising:

providing a wafer having a gate electrode material layer formed thereabove;

forming a patterned layer of photoresist above the gate electrode material layer;

performing a photoresist etching process on the patterned layer of photoresist;

etching the gate electrode material layer using the etched patterned layer of photoresist as a mask to define a plurality of patterned features;

measuring a critical dimension of a plurality of said patterned features; and

controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of patterned features.

64. The method of claim 63, wherein forming a patterned layer of photoresist above the gate electrode material layer comprises forming a patterned layer of photoresist above the gate electrode material layer by performing at least an exposure process, a post-exposure bake process and a photoresist develop process.

65. The method of claim 63, wherein measuring a critical dimension of a plurality of patterned features comprises measuring a critical dimension of a plurality of patterned features by using at least one of scanning electron microscopy, image shearing, and reflective measurements.

66. The method of claim 63, further comprising storing said measured critical dimensions in a database.

67. The method of claim 63, further comprising feeding back the measured critical dimensions of the plurality of patterned features to a process model.

68. The method of claim 67, further comprising filtering the measured critical dimensions prior to feeding back the measured critical dimensions to the process model.

69. The method of claim 63, wherein controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension of said plurality of patterned features comprises controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a quadratic relationship between the measured critical dimensions and a duration of the photoresist etch process.

70. The method of claim 63, further comprising measuring a critical dimension of a plurality of features formed in said patterned layer of photoresist prior to performing said photoresist etching process.

71. The method of claim 70, wherein controlling at least one parameter of a photoresist etching process comprises controlling at least one parameter of said photoresist etching process based upon said measured critical dimension of said plurality of patterned features, said measured critical dimension of said plurality of features in said patterned layer of photoresist, and said target value for said plurality of patterned features.

72. The method of claim 63, wherein etching the gate electrode material layer using the etched patterned layer of photoresist as a mask to define a plurality of patterned features comprises etching the gate electrode material layer using the etched patterned layer of photoresist as a mask to define a plurality of gate electrodes.

73. The method of claim 70, wherein measuring a critical dimension of a plurality of said patterned features comprises measuring a critical dimension of a plurality of said gate electrodes.

74. The method of claim 63, wherein controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of patterned features comprises controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of patterned features.

75. A method of fabricating an integrated circuit device, comprising:

providing a wafer having a gate electrode material layer formed thereabove;

forming a patterned layer of photoresist above the gate electrode material layer;

performing a photoresist etching process on the patterned layer of photoresist;

etching the gate electrode material layer using the etched patterned layer of photoresist as a mask to define a plurality of patterned features;

measuring a critical dimension of a plurality of said patterned features;

feeding back the measured critical dimensions of the plurality of patterned features to a process model; and

controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of patterned features.

76. The method of claim 75, wherein forming a patterned layer of photoresist above the gate electrode material layer comprises forming a patterned layer of photoresist above the gate electrode material layer by performing at least an exposure process, a post-exposure bake process and a photoresist develop process.

77. The method of claim 75, wherein measuring a critical dimension of a plurality of patterned features comprises measuring a critical dimension of a plurality of patterned features by using at least one of scanning electron microscopy, image shearing, and reflective measurements.

78. The method of claim 75, further comprising filtering the measured critical dimensions prior to feeding back the measured critical dimensions to the process model.

79. The method of claim 75, wherein controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of patterned features comprises controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a quadratic relationship between the measured critical dimensions and a duration of the photoresist etch process.

80. The method of claim 75, further comprising storing said measured critical dimensions in a database.

81. The method of claim 75, further comprising measuring a critical dimension of at least one feature formed in said patterned layer of photoresist prior to performing said photoresist etching process.

82. The method of claim 81, wherein controlling at least one parameter of a photoresist etching process comprises controlling at least one parameter of said photoresist etching process based upon said measured critical dimension of a plurality of said patterned features, said measured critical dimension of said at least one feature in said patterned layer of photoresist, and said target value for said patterned features.

83. The method of claim 75, wherein etching the gate electrode material layer using the etched patterned layer of photoresist as a mask to define a plurality of patterned features comprises etching the gate electrode material layer using the etched patterned layer of photoresist as a mask to define a plurality of gate electrodes.

84. The method of claim 83, wherein measuring a critical dimension of a plurality of said patterned features comprises measuring a critical dimension of a plurality of said gate electrodes.

85. The method of claim 83, wherein feeding back the measured critical dimensions of the plurality of patterned features to a process model comprises feeding back the measured critical dimensions of the plurality of gate electrodes to a process model.

86. The method of claim 75, wherein controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of patterned features comprises controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of patterned features.

87. A method of fabricating an integrated circuit device, comprising:

providing a wafer having a gate electrode material layer formed thereabove;

forming a patterned layer of photoresist above the gate electrode material layer, said patterned layer of photoresist having a plurality of features formed therein;

measuring a critical dimension of at least one of said features in said patterned layer of photoresist prior to performing a photoresist etching process on said patterned layer of photoresist; and

controlling a duration of said photoresist etching process based upon at least said measured critical dimension of said at least one feature in said patterned layer of photoresist.

88. The method of claim 87, further comprising etching said gate electrode material layer after said photoresist etching process has been performed using said patterned layer of photoresist as a mask to thereby define at least one feature in said gate electrode material layer.

89. The method of claim 88, further comprising measuring a critical dimension of at least one of said features in said gate electrode material layer.

90. The method of claim 88, wherein said at least one feature in said gate electrode material layer is a gate electrode.

91. A method of fabricating an integrated circuit device, comprising:

providing a wafer having a gate electrode material layer formed thereabove;

forming a patterned layer of photoresist above the gate electrode material layer, said layer of photoresist having a plurality of features formed therein;

measuring a critical dimension of at least one of said features in said patterned layer of photoresist prior to performing a photoresist etching process on said patterned layer of photoresist;

determining a duration of said photoresist etching process based upon at least said measured critical dimension of said at least one feature in said patterned layer of photoresist; and

performing said photoresist etch process for said determined duration on a patterned layer of photoresist formed above at least one subsequently processed wafer.

92. The method of claim 91, further comprising etching said gate electrode material layer after said photoresist etching process has been performed to thereby define at least one feature in said gate electrode material layer.

93. The method of claim 92, further comprising measuring a critical dimension of at least one of said features in said gate electrode material layer.

94. The method of claim 92, wherein said at least one feature in said gate electrode material layer is a gate electrode.

95. A method of fabricating an integrated circuit device, comprising:

providing a wafer having a gate electrode material layer formed thereabove;

forming a patterned layer of photoresist above the gate electrode material layer, said patterned layer of photoresist having a plurality of features formed therein;

measuring a critical dimension of at least one of said features in said patterned layer of photoresist prior to performing a photoresist etching process on said patterned layer of photoresist; and

controlling at least one parameter of said photoresist etching process based upon at least said measured critical dimension of said at least one feature in said patterned layer of photoresist.

96. The method of claim 95, further comprising etching said gate electrode material layer after said photoresist etching process has been performed using said patterned layer of photoresist as a mask to thereby define at least one feature in said gate electrode material layer.

97. The method of claim 96, further comprising measuring a critical dimension of at least one of said features in said gate electrode material layer.

98. The method of claim 96, wherein said at least one feature in said gate electrode material layer is a gate electrode.

99. The method of claim 95, wherein said at least one parameter comprises at least one of RF power, a gas flow rate and a chamber pressure.

100. A method of fabricating an integrated circuit device, comprising:

providing a wafer having a gate electrode material layer formed thereabove;

forming a patterned layer of photoresist above the gate electrode material layer, said layer of photoresist having a plurality of features formed therein;

measuring a critical dimension of at least one of said features in said patterned layer of photoresist prior to performing a photoresist etching process on said patterned layer of photoresist;

determining at least one parameter of said photoresist etching process based upon at least said measured critical dimension of said at least one feature in said patterned layer of photoresist; and

performing said photoresist etch process for said determined duration on a patterned layer of photoresist formed above at least one subsequently process wafer.

101. The method of claim 100, further comprising etching said gate electrode material layer after said photoresist etching process has been performed to thereby define at least one feature in said gate electrode material layer.

102. The method of claim 101, further comprising measuring a critical dimension of at least one of said features in said gate electrode material layer.

103. The method of claim 101, wherein said at least one feature in said gate electrode material layer is a gate electrode.

104. The method of claim 100, wherein said at least one parameter comprises at least one of RF power, a gas flow rate and a chamber pressure.