Twin p-well CMOS imager
First Claim
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1. An imaging device comprising:
- a substrate;
a photosensitive area within a first p-well formed in said substrate for accumulating photo-generated charge in said area; and
a periphery logic area within in a second p-well in said substrate; and
a n-well disposed between said first and second p-wells,wherein said first p-well is deeper than said second p-well and said second p-well is doped to a higher ion concentration than said first p-well.
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Abstract
A CMOS imager which includes a substrate voltage pump to bias a doped area of a substrate to prevent leakage into the substrate from the transistors formed in the doped area. The invention also provides a CMOS imager where a photodetector sensor array is formed in a first p-well and readout logic is formed in a second p-well. The first p-well can be selectively doped to optimize cross-talk, collection efficiency and transistor leakage, thereby improving the quantum efficiency of the sensor array while the second p-well can be selectively doped and/or biased to improve the speed and drive of the readout circuitry.
28 Citations
82 Claims
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1. An imaging device comprising:
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a substrate; a photosensitive area within a first p-well formed in said substrate for accumulating photo-generated charge in said area; and a periphery logic area within in a second p-well in said substrate; and a n-well disposed between said first and second p-wells, wherein said first p-well is deeper than said second p-well and said second p-well is doped to a higher ion concentration than said first p-well. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. An imaging device including a semiconductor integrated circuit substrate, said imaging device comprising:
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a photosensitive device formed in a first p-well in said substrate for accumulating photo-generated charge in an underlying portion of said substrate, said photosensitive device comprising a first transistor; a periphery logic area formed in a second p-well in said substrate, said periphery logic area comprising a second transistor; and a n-well disposed between said first and second p-wells, wherein said first transistor has a higher threshold voltage than said second transistor, said first p-well is deeper than said second p-well, and said second p-well is doped to a higher ion concentration than said first p-well. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53)
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54. An imaging system comprising:
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a processor; and a CMOS imaging device coupled to said processor and including; a photosensitive area within a first p-well in a substrate for accumulating photo-generated charge in said area; a periphery logic area formed in a second p-well in said substrate; and a n-well disposed between said first and second p-wells, wherein said first p-well is doped to a greater depth than said second p-well and said second p-well is doped to a higher ion concentration than said first p-well. - View Dependent Claims (55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79)
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80. A CMOS imager, comprising:
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a pixel array comprising a pixel coupled to a column output line to provide a pixel output signal to the column output line, the pixel including a first n-channel reset transistor comprising a first p-well region of the array, wherein the first n-channel reset transistor has a first threshold voltage; a peripheral region, including a readout circuit coupled to the column output line, to receive the pixel output signal from the array, the peripheral region including a second n-channel transistor including a second p-well region of the periphery and a p-channel transistor including an n-well region of the periphery, wherein the second n-channel transistor has a second threshold voltage that is independent from the first threshold voltage, and the n-well region is disposed between the first and second p-well regions; and a voltage pump to provide a negative voltage to the first n-channel reset transistor to turn off the n-channel reset transistor. - View Dependent Claims (81, 82)
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Specification
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Current AssigneeRound Rock Research LLC
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Original AssigneeRound Rock Research LLC
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InventorsRhodes, Howard E.
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Primary Examiner(s)SANDVIK, BENJAMIN P
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Application NumberUS12/714,339Time in Patent Office1,803 DaysField of SearchNoneUS Class Current257/291CPC Class CodesH01L 27/14609 Pixel-elements with integra...
