Output delay circuit

Output delay circuit

  • CN 100,334,805 C
  • Filed: 07/29/1998
  • Issued: 08/29/2007
  • Est. Priority Date: 07/29/1997
  • Status: Active Grant
First Claim
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1. an output delay circuit is characterized in that, this output delay circuit comprises:

  • First logical circuit (4), input has the input signal and the input clock pulse of first logic state and second logic state to this first logical circuit (4), when having at least one to be in first logic state in this input signal and the input clock pulse, output signal of this first logical circuit (4) output with first logic state;

    Second logical circuit (5), the output signal of described first logical circuit (4) is imported into an input in two inputs of this second logical circuit (5), when having at least one to be in first logic state in two input signals of this second logical circuit (5), output signal of this second logical circuit (5) output with first logic state;

    A counter (1), the output signal of described second logical circuit (5) is imported into the input end of clock of this counter (1), and the described input signal of described first logical circuit (4) is input to the reset terminal of this counter (1) after anti-phase by one first inverter (7), when the described input signal of described first logical circuit (4) is being in when being transfused under described first logic state, described counter (1) is reset, and be in when being transfused under described second logic state when described input signal, the clock pulse that is input to its input end of clock is counted;

    A comparator (2), be connected to described counter (1), be used for that the cumulative number of clock pulse that described counter (1) has been counted preestablishes with one and compare with the predetermined clock number that external mode is input to described comparator (2), according to output signal of comparative result output, the output signal of this comparator (3) is input to another input in two inputs of described second logical circuit (5) after anti-phase by one second inverter (8), be used for stopping when the cumulative number of described input clock pulse and described predetermined clock number are consistent with each other the counting operation of described counter (1);

    AndOutput device (6), an one input is connected to the output of described comparator (2), the described input signal that is input to described first logical circuit (4) also is imported into another input of this output device, this output device (6) is used for when the cumulative number of having determined described clock pulse by described comparator (2) during less than predetermined clock number, export an output signal that has with the described first logic state equal state, be used for simultaneously when having determined that by described comparator the cumulative number of input clock pulse is not less than predetermined clock number, export an output signal that has with the described second logic state same signal state.

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