Memory cell design with vertically stacked crossovers

Memory cell design with vertically stacked crossovers

  • CN 100,388,499 C
  • Filed: 03/20/1997
  • Issued: 05/14/2008
  • Est. Priority Date: 03/28/1996
  • Status: Active Grant
First Claim
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1. semiconductor memory cell comprises:

  • First gate with first input and first output;

    Second gate with second input and second output;

    Comprise the grid layer that first cross-over connection connects, described first cross-over connection connects direct the input described first and is connected to described second output;

    AndComprise the metal interconnecting layer that second cross-over connection connects, described second cross-over connection connects direct the input described second and is connected to described first output, described second cross-over connection is connected to form on described first cross-over connection of part connects and is not connected with described first cross-over connection and contacts, so that look from the top, described first and second cross-over connections connect overlapping.

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