Semiconductor device of laminated chips

Semiconductor device of laminated chips

  • CN 100,524,744 C
  • Filed: 05/31/2002
  • Issued: 08/05/2009
  • Est. Priority Date: 06/01/2001
  • Status: Active Grant
First Claim
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1. , a kind of semiconductor device of chip stacking is characterized in that comprising:

  • Have a plurality of semiconductor chips of many barss with terminal;

    Along the stacked multi-plate chip installation base plate more than 2 layers of thickness direction, on each chip mounting substrate, install respectively in the above-mentioned semiconductor chip more than 1, many the chips that above-mentioned each signal that is formed with each semiconductor chip that is mounted with this is electrically connected with terminal are connected the usefulness distribution and are connected with chip and use the path terminal, andBe formed with many interlayers connections that are connected with the wired electric connection with above-mentioned each chip of adjacent said chip installation base plate and be connected at least 2 Intermediate substrates using the path terminal with distribution with interlayer, described at least 2 Intermediate substrates and above-mentioned multi-plate chip installation base plate alternate configurationsAbove-mentioned each chip connection forms identical pattern with distribution for above-mentioned each chip mounting substrate, simultaneously, above-mentioned each interlayer connects with distribution and forms mutually different pattern for each of above-mentioned at least 2 Intermediate substrates, and above-mentioned each chip connection of adjacent above-mentioned each chip mounting substrate is connected with above-mentioned each interlayer of above-mentioned each Intermediate substrate with distribution with distribution uses path terminal or above-mentioned each interlayer connection to be electrically connected with the path terminal by above-mentioned each chip connection, and above-mentioned each interlayer that is configured in above-mentioned each Intermediate substrate in the different layers connects to connect to connect with path terminal and above-mentioned each chip of being configured in above-mentioned each chip mounting substrate between above-mentioned each Intermediate substrate with above-mentioned each interlayer by above-mentioned each Intermediate substrate between the wiring uses the electrical connection of path terminalAbove-mentioned each interlayer connection forms at least a pattern that can switch in following two kinds of status of electrically connecting with distribution, promptly, above-mentioned each signal between above-mentioned each semiconductor chip that is installed in respectively on above-mentioned each chip mounting substrate is with terminal status of electrically connecting each other, or many outside terminals that are electrically connected to a plurality of predetermined external terminals connect with distributions and above-mentioned each signal status of electrically connecting with terminal.

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