Memory command delay balancing in a daisy-chained memory topology

Memory command delay balancing in a daisy-chained memory topology

  • CN 101,014,941 A
  • Filed: 08/09/2005
  • Published: 08/08/2007
  • Est. Priority Date: 08/19/2004
  • Status: Active Grant
First Claim
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1. method comprises:

  • Connect a plurality of memory modules with daisy-chained configuration, wherein, each of described a plurality of memory modules comprises corresponding a plurality of memory element;

    Receive instruction on one in described a plurality of memory modules;

    Give one or more memory modules in the described daisy-chained configuration with described diffusion of instructions;

    AndIn described a plurality of memory modules at least one is configured to, postpones the transmission of one or more memory elements of wherein comprising to it in the instruction of this reception, up to having passed through corresponding first preset delay.

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