Memory command delay balancing in a daisy-chained memory topology

Memory command delay balancing in a daisy-chained memory topology

  • CN 101,014,941 B
  • Filed: 08/09/2005
  • Issued: 03/06/2013
  • Est. Priority Date: 08/19/2004
  • Status: Active Grant
First Claim
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1. order the delay equalization method for one kind, comprising:

  • Connect a plurality of memory modules with daisy-chained configuration, wherein, each of described a plurality of memory modules comprises corresponding a plurality of memory element;

    One in described a plurality of memory modules receives instruction;

    Give one or more memory modules in the described daisy-chained configuration with described diffusion of instructions;

    AndIn described a plurality of memory modules at least one is configured to postpone to carry out the described instruction that is received by the one or more memory elements that wherein comprise, until passed through corresponding first preset delay, so that standardization is carried out with the described instruction on described a plurality of memory modules of described daisy-chained configuration.

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