Scalable integrated logic and non-volatile memory

Scalable integrated logic and non-volatile memory

  • CN 101,061,585 B
  • Filed: 11/01/2005
  • Issued: 04/18/2012
  • Est. Priority Date: 11/23/2004
  • Status: Active Grant
First Claim
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1. scalable non-volatile transistor, it comprises:

  • Substrate, it comprises a plurality of doped regions;

    Gate insulator;

    It is formed on the said substrate and is in fact between said a plurality of doped region;

    Wherein said gate insulator further comprises a SiON layer and has the physical thickness in the 2.0-2.5nm scope that said physical thickness has the equivalent oxide thickness in the 1.0-1.5nm scope;

    High dielectric constant insulator with embedded metallic nanodots, it is formed on said gate insulator top;

    WithGate stack, it is formed on said high dielectric constant insulator top and comprises;

    Metal nitride layer, it is formed on said high dielectric constant insulator top;

    Grid layer, it is formed on said metal nitride layer top;

    WithMetal silicide layer, it is formed on said grid layer top.

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