Memory module

Memory module

  • CN 101,075,217 B
  • Filed: 05/16/2007
  • Issued: 03/18/2015
  • Est. Priority Date: 05/16/2006
  • Status: Active Grant
First Claim
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1. a memory module, is connected in series multiple memory device and forms, and the plurality of memory device comprises first memory part and second memory part, it is characterized in that:

  • Form each memory device receiving package of multiple memory devices of above-mentioned memory module containing the request represented the identifying information of the request of which memory device in above-mentioned multiple memory device, and when responding above-mentioned request, the identifying information comprising above-mentioned memory device exportsAbove-mentioned response is carried out according to the priority of response,Above-mentioned second memory part is connected to the rear class of above-mentioned first memory part;

    Above-mentioned first memory part sends in above-mentioned request the above-mentioned identifying information comprised to above-mentioned second memory part, and receives the above-mentioned identifying information comprised in the response of above-mentioned second memory part output,Any one in the order of restarting of the change of the clock frequency of carrying out memory device, the stopping of clock, clock is comprised in above-mentioned request,Described first memory part has;

    The first memory circuit of storage information;

    First request queue control circuit, the first request signal is sent to described first memory circuit from signal conditioning package by it, from described signal conditioning package, the second request signal is sent to described second memory part;

    AndFirst response queue'"'"'s control circuit, the first response signal is outputted to described signal conditioning package by it, and the second response signal is sent to described signal conditioning package from described second memory part,Described second memory part has;

    The second memory circuit of storage information;

    Second request queue control circuit, described second request signal is sent to described second memory circuit by it;

    AndSecond response queue'"'"'s control circuit, described second response signal is outputted to described first memory part by it,Described first request signal comprises and represents that the request target of described first request signal is the first identifying information of described first memory part,Described second request signal comprises and represents that the request target of described second request signal is the second identifying information of described second memory part,Described first response signal comprises and represents that the transfer source of described first response signal is the 3rd identifying information of described first memory part,Described second response signal comprises and represents that the transfer source of described second response signal is the 4th identifying information of described second memory part.

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