In a wireless communication system data are carried out to the method and apparatus of despreading

In a wireless communication system data are carried out to the method and apparatus of despreading

  • CN 101,142,755 B
  • Filed: 01/19/2006
  • Issued: 08/26/2015
  • Est. Priority Date: 01/31/2005
  • Status: Active Grant
First Claim
Patent Images

1. , for carrying out a method for despreading in the receiver of wireless communication system to spread-spectrum signal, comprise step:

  • Carry out preliminary treatment to spread-spectrum signal, to derive spread-spectrum code chip group, described spread-spectrum code chip group is corresponding with data symbol;

    Process described spread-spectrum code chip, to extract in-phase component and the quadrature component of each spread-spectrum code chip, described in-phase component and described quadrature component are divided into odd component and even component respectively;

    Based on preset selecting signal, the group of the odd, even component of homophase and orthogonal odd, even component is changed and combined, to derive despreading chip set;

    Wherein, described preset selecting signal is the sign function of the conjugation of frequency expansion sequence;

    Wherein, described conversion and anabolic process comprise step;

    -for the first branch circuit, orthogonal odd component is inputted successively the first input end of multiple selector, by second input of described orthogonal odd component by the result input selector of negate device gained, described selector is based on the sign function value of the conjugation of the frequency expansion sequence inputted in selecting side, correspondingly select and export the signal inputted at described first input end or the signal inputted at described second input, the output of the output of each selector and upper level selector is sued for peace, after postponed a clock cycle by delayer, export summed result, prime of working as described first branch circuit exports, and the output of this output and next stage selector is sued for peace, until the most final stage of described first branch circuit, obtain result first real part of described first branch circuit,-for the second branch circuit, homophase even component is inputted successively the second input of multiple selector, by the first input end of described homophase even component by the result input selector of negate device gained, described selector is based on the sign function value of the conjugation of the frequency expansion sequence inputted in selecting side, correspondingly select and export the signal inputted at described first input end or the signal inputted at described second input, the output of the output of each selector and upper level selector is sued for peace, after postponed a clock cycle by delayer, export summed result, prime of working as described second branch circuit exports, and the output of this output and next stage selector is sued for peace, until the most final stage of described second branch circuit, obtain result second real part of described second branch circuit,-for the 3rd branch circuit, homophase odd component is inputted successively the second input of multiple selector, by the first input end of described homophase odd component by the result input selector of negate device gained, described selector is based on the sign function value of the conjugation of the frequency expansion sequence inputted in selecting side, correspondingly select and export the signal inputted at described first input end or the signal inputted at described second input, the output of the output of each selector and upper level selector is sued for peace, after postponed a clock cycle by delayer, export summed result, prime of working as described 3rd branch circuit exports, and the output of this output and next stage selector is sued for peace, until the most final stage of described 3rd branch circuit, obtain result first imaginary part of described 3rd branch circuit,-for the 4th branch circuit, Orthogonal-even component is inputted successively the second input of multiple selector, by the first input end of described Orthogonal-even component by the result input selector of negate device gained, described selector is based on the sign function value of the conjugation of the frequency expansion sequence inputted in selecting side, correspondingly select and export the signal inputted at described first input end or the signal inputted at described second input, the output of the output of each selector and upper level selector is sued for peace, after postponed a clock cycle by delayer, export summed result, prime of working as described 4th branch circuit exports, and the output of this output and next stage selector is sued for peace, until the most final stage of described 4th branch circuit, obtain result second imaginary part of described 4th branch circuit,Or-for the first branch circuit, orthogonal odd component is inputted multiple ALU (ALU), described multiple ALU receives the odd positions value of the conjugate of symbol from frequency expansion sequence simultaneously, and described multiple ALU cascades with one another;

    -for the second branch circuit, homophase even component is inputted multiple ALU, and described multiple ALU receives the even number positional value of the conjugate of symbol from frequency expansion sequence simultaneously, and described multiple ALU cascades with one another;

    -for the 3rd branch circuit, homophase odd component is inputted multiple ALU, and described multiple ALU receives the odd positions value of the conjugate of symbol from frequency expansion sequence simultaneously, and described multiple ALU cascades with one another;

    -for the 4th branch circuit, Orthogonal-even component is inputted multiple ALU, and described multiple ALU receives the even number positional value of the conjugate of symbol from frequency expansion sequence simultaneously, and described multiple ALU cascades with one another;

    -wherein, the result that the most final stage ALU of described first branch circuit exports is the first real part, and the result that the most final stage ALU of described second branch circuit exports is the second real part;

    The result that the most final stage ALU of described 3rd branch circuit exports is the first imaginary part, and the result that the most final stage ALU of described 4th branch circuit exports is the second imaginary part;

    -wherein, described ALU comprises negate device, selector, adder and delayer, described selector comprises and inputting for the selection received from the conjugate of symbol value of frequency expansion sequence, be connected with the output of described negate device first inputs, and to be connected with the input of described negate device second inputs, described selector is based on the described value selecting input, correspondingly select the value of described first input or described second input input, homophase, quadrature component strange, even component is as the second input of described selector, the output of described selector is connected with the input of described adder, output from upper level ALU is input to another input of described adder, the output of described adder is connected with described delayer, and export from output after postponing a clock cycle by described delayer,Wherein, the value of the spreading code in frequency expansion sequence is in known finite aggregate.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×