RISC processor device as well as bound visit storage method thereof

RISC processor device as well as bound visit storage method thereof

  • CN 101,226,468 A
  • Filed: 01/30/2008
  • Published: 07/23/2008
  • Est. Priority Date: 01/30/2008
  • Status: Active Application
First Claim
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1. a risc processor device comprises the physical register heap, and code translator and arithmetic unit is characterized in that:

  • Described physical register heap comprises boundary address register, is used to store the effective address as the upper bound;

    And following boundary address register, be used to store effective address as lower bound;

    Described arithmetic unit comprises first judge module, is used in access instruction, according to the following limit address of storing in last limit address of storing in the last boundary address register and/or the following boundary address register, the validity of decision instruction operand address.

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