Asynchronous line interface rate adaptation to the physical layer with synchronous lines at the connection layer

Asynchronous line interface rate adaptation to the physical layer with synchronous lines at the connection layer

  • CN 101,313,500 A
  • Filed: 09/20/2006
  • Published: 11/26/2008
  • Est. Priority Date: 09/21/2005
  • Status: Active Application
First Claim
Patent Images

1. the single clock zone of rate adapted of asynchronous HDLC channel (15) that is used to make some is so that be adapted to pass through the method that pseudo-TDM sync cap (14) is docked with HDLC processor (13), wherein multiplexing in time described channel, and wherein with the corresponding clock of described channels associated after described HDLC asynchronous channel is respectively write buffer (17) with each HDLC channels associated, and read these buffers with the common synchronous of the maximum HDLC speed of a little higher than expectation, and when this being judged by buffer filling monitoring function, insert average information, to avoid the underrun condition.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×