Ultra-thin wafer-level contact grid array

Ultra-thin wafer-level contact grid array

  • CN 101,339,929 B
  • Filed: 11/29/2007
  • Issued: 06/26/2013
  • Est. Priority Date: 07/02/2007
  • Status: Active Grant
First Claim
Patent Images

1. crystal plate grade chip size encapsulating structure comprises:

  • The semiconductor die package body;

    A plurality of protrusions, be formed on described semiconductor die package body thereby be deposited in the face array on the grain surface in described semiconductor die package body, and comprise block on the top that extends described semiconductor die package body, be used for providing electric connection between printed circuit board (PCB) and this semiconductor die package body, wherein each protrusion of these a plurality of protrusions is not more than the surface 10 μ

    m higher than this semiconductor die package body;

    One heavy distribution layer is included in described semiconductor die package body, and provides between the active part of described semiconductor die package body and described a plurality of protrusions and be connected, and wherein said a plurality of protrusions directly and described heavy distribution layer electrical contact and physical contact;

    AndA plurality of welding rods are arranged on the corner of this die package body, and wherein each welding rod of these a plurality of welding rods is not more than the surface 10 μ

    m higher than this semiconductor die package body.

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