Charge trapping memory cell with high speed erase

Charge trapping memory cell with high speed erase

  • CN 101,369,583 A
  • Filed: 05/13/2008
  • Published: 02/18/2009
  • Est. Priority Date: 08/13/2007
  • Status: Active Application
First Claim
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1. a charge capturing memory is characterized in that, comprising:

  • One memory cell array, each memory cell in this memory cell array comprises;

    Semi-conductive substrate comprises a raceway groove, and this raceway groove has a channel surface;

    One tunnel dielectric layer, be arranged on this channel surface, this tunnel dielectric layer is the combination of a plurality of materials, and the mode that forms a relatively large tunneled holes potential barrier with contiguous this channel surface place disposes, have the valence-band level of increase in one first deviation post that leaves this channel surface, have the valence-band level of reduction in leaving one second deviation post of this channel surface greater than 2 nanometers;

    One charge-trapping dielectric layers is arranged on this tunnel dielectric layer;

    One stops dielectric layer, is arranged on this charge-trapping dielectric layers, and this stops that dielectric layer comprises that dielectric constant k is more than or equal to a material of 7;

    AndOne grid is arranged at this and stops on the dielectric layer, and this grid comprises that being arranged at this stops a metal or metallic compound on the dielectric layer.

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