System and method for flushing a cache line in response to instruction

System and method for flushing a cache line in response to instruction

  • CN 101,446,923 B
  • Filed: 12/28/2000
  • Issued: 06/24/2015
  • Est. Priority Date: 12/30/1999
  • Status: Active Grant
First Claim
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1. clean a device for cache line in response to instruction, it is characterized in that, this device comprises:

  • The first cache memory in coherence domains;

    The second cache memory in described coherence domains;

    AndCache controller, it is for receiving the storage address specified by the operand of described instruction, described cache controller is in response to described instruction, clean first cache line relevant to the described storage address be stored in described first cache memory, wherein find that described first cache line is in the wherein a kind of state in single user state and shared state, andBus controller, bus sends bus inefficiencies affairs.

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