Grid and manufacturing method for transistor

Grid and manufacturing method for transistor

  • CN 101,459,134 A
  • Filed: 12/13/2007
  • Published: 06/17/2009
  • Est. Priority Date: 12/13/2007
  • Status: Active Grant
First Claim
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1. the manufacture method of a grid is characterized in that, comprising:

  • Form gate dielectric layer and polysilicon layer on Semiconductor substrate successively, described Semiconductor substrate is divided into device compact district and device non-dense set district;

    Etch polysilicon layer and gate dielectric layer form grid to exposing Semiconductor substrate;

    The etching grid makes the grid critical size of device compact district consistent with the grid critical size in device non-dense set district, reaches target size.

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