Grid and manufacturing method for transistor

Grid and manufacturing method for transistor

  • CN 101,459,134 B
  • Filed: 12/13/2007
  • Issued: 07/11/2012
  • Est. Priority Date: 12/13/2007
  • Status: Active Grant
First Claim
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1. the manufacture method of a grid is characterized in that, comprising:

  • On Semiconductor substrate, form gate dielectric layer and polysilicon layer successively, said Semiconductor substrate is divided into device compact district and device non-dense set district;

    Etch polysilicon layer and gate dielectric layer form grid to exposing Semiconductor substrate, and the grid critical size in the grid of said device compact district and device non-dense set district is all greater than target size;

    The etching grid makes the grid critical size of device compact district consistent with the grid critical size in device non-dense set district, reaches target size;

    The grid critical size that the gas of etch polysilicon layer and gate dielectric layer makes the device compact district is than the grid critical size in device non-dense set district hour, and the grid critical size that the gas of etching grid changes than device non-dense set district the grid critical size of device compact district changes little;

    When perhaps the gas of etch polysilicon layer and the gate dielectric layer grid critical size that makes the device compact district was bigger than the grid critical size in device non-dense set district, the grid critical size that the gas of etching grid changes than device non-dense set district the grid critical size of device compact district changed greatly.

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