Singleprecision floatingpoint data storing method and processor
Singleprecision floatingpoint data storing method and processor
 CN 101,539,850 B
 Filed: 11/27/2008
 Issued: 04/01/2015
 Est. Priority Date: 03/21/2008
 Status: Active Grant
First Claim
1. the singleprecision floatingpoint data storing method used in the processor comprising register, described register has the size that can store doubleprecision floating point data, and for storing doubleprecision floating point data and singleprecision floatingpoint data, described method comprises:
 If specify singleprecision floatingpoint data process and specify the first process, then to the singleprecision floatingpoint data of the high half write input of described register, and the low level half part all writes zero to described register;
If specify singleprecision floatingpoint data process and specify the second process, then to the singleprecision floatingpoint data of the high half write input of described register, and data are not write to low level half part of described register;
Decoding is carried out to instruction, and performs the writing process to register according to the decode results of this instruction;
Before data are written into register, in rename register, temporarily store the data corresponding to described first process and/or described second process;
If specify the first process, then write the data of rename register;
AndIf specify the second process, if the destination address of writing being included in the register in decode results is even number, then the data of the high half of rename register are write the high half of register, if the destination address of writing of register is odd number, then the data of the high half of rename register are write low level half part of register.
Chinese PRB Reexamination
Abstract
A singleprecision floatingpoint data storing method for use in a processor including a register, which has a size that can store doubleprecision floatingpoint data, for storing doubleprecision floatingpoint data and singleprecision floatingpoint data comprises writing input singleprecision floatingpoint data to the highorder half of the register, and writing all zeros to the loworder half of the register if a singleprecision floatingpoint data process is specified.
7 Claims

1. the singleprecision floatingpoint data storing method used in the processor comprising register, described register has the size that can store doubleprecision floating point data, and for storing doubleprecision floating point data and singleprecision floatingpoint data, described method comprises:

If specify singleprecision floatingpoint data process and specify the first process, then to the singleprecision floatingpoint data of the high half write input of described register, and the low level half part all writes zero to described register; If specify singleprecision floatingpoint data process and specify the second process, then to the singleprecision floatingpoint data of the high half write input of described register, and data are not write to low level half part of described register; Decoding is carried out to instruction, and performs the writing process to register according to the decode results of this instruction; Before data are written into register, in rename register, temporarily store the data corresponding to described first process and/or described second process; If specify the first process, then write the data of rename register;
AndIf specify the second process, if the destination address of writing being included in the register in decode results is even number, then the data of the high half of rename register are write the high half of register, if the destination address of writing of register is odd number, then the data of the high half of rename register are write low level half part of register.


2. a processor, comprising:

Register, it has the size that can store doubleprecision floating point data, for storing doubleprecision floating point data and singleprecision floatingpoint data; Control module, if for specifying singleprecision floatingpoint data process and specifying the first process, then write the high half of singleprecision floatingpoint data to register of input, and the low level half part all writes zero to register, if or for specifying singleprecision floatingpoint data process and specifying the second process, then write the high half of singleprecision floatingpoint data to register of input, and do not write data to low level half part of register; For the code translator to Instruction decoding, wherein control module performs writing process to register according to code translator to the decode results of instruction; Rename register, temporarily stored the data corresponding to the first process or the second process before being written into register in data;
AndSubmission control unit, write destination address, and for submitting data storage in a register to, these data is stored in rename register, wherein for arranging by the control signal of the instruction of decoder for decoding and register If specify the first process, then write the data of rename register unchangeably, and If specify the second process, if the destination address of writing of the register arranged by Submission control unit is even number, then write the high half of data to register of the high half of rename register, if the destination address of writing of register is odd number, then write low level half part of data to register of the high half of rename register.


3. processor as claimed in claim 2, also comprises and is used to specify the first process or the second process and the second register keeping appointed information.

4. processor as claimed in claim 3, wherein
Second register is the arithmetic register of expansion, and whether effectively determines that process is the first process or the second process according to the arithmetic register of this expansion.

5. processor as claimed in claim 3, also comprises:

Code translator, for carrying out decoding to instruction, wherein When decoder for decoding is for ordering the instruction carrying out singleprecision floating point arithmetic processing or the process of singleprecision floating point load/store, according to the appointment of the second register, with the unit of singleprecision floatingpoint data or with the unit order read/write register address of doubleprecision floating point data.


6. processor as claimed in claim 3, also comprises:

For the code translator to Instruction decoding; For performing the arithmetic processing unit of arithmetic processing;
AndFor performing the loading processing unit of loading processing, wherein When decoding is for ordering the instruction carrying out singleprecision floating point arithmetic processing or singleprecision floating point loading processing, code translator corresponds to the first process and second and processes and transmit common operational code to arithmetic processing unit and loading processing unit, and Arithmetic processing unit and loading processing unit to the high half Output rusults of register, and all export zero to low level half part.


7. processor as claimed in claim 3, also comprises:

For the code translator to Instruction decoding; For performing the arithmetic processing unit of arithmetic processing;
AndFor performing the storage processing unit of stores processor, wherein When decoding is for ordering the instruction carrying out singleprecision floating point arithmetic processing or singleprecision floating point stores processor, code translator corresponds to the first process and second and processes and transmit common operational code to arithmetic processing unit and storage processing unit, and By only using the data of the length of the high half of register as input, arithmetic processing unit and storage processing unit perform arithmetic processing and stores processor respectively.

Specification(s)