Multi-threaded architecture

Multi-threaded architecture

  • CN 101,627,365 B
  • Filed: 11/14/2007
  • Issued: 03/29/2017
  • Est. Priority Date: 11/14/2006
  • Status: Active Grant
First Claim
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1. a kind of multi-threaded architecture, which includes:

  • Register set;

    Performance element collection;

    Circuit, which is used to adjust the register set and performance element collection, support instruction level parallelism and software thread andHardware generates the execution of thread;

    Scheduling unit, for one group of instruction of instruction is received with independent instruction and be mutually associated from sequencer program, and usesInherit vector and dispatch group instruction, wherein being utilized for being brought into what is performed in performance element from the information for inheriting vectorThe group instruction filling correlation information;

    Wherein described performance element collection processes the group and instructs, and accesses multiple register file segments of the register set, instituteIt is physical segment to state multiple register file segments, but shows as having shared register number in each register file segmentUnified architecture resources, wherein the hardware thread identifier specified using sets of numbers and dynamic, shared register number is solvedAnalyse as single register file segment;

    Wherein the hardware generate thread be in response in the group instruct and what dynamic was specified, and the hardware generates thread and supportsThe concurrently execution of the different piece of the sequencer program.

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