Integrated circuit and its power management method

Integrated circuit and its power management method

  • CN 101,662,276 A
  • Filed: 07/05/2005
  • Published: 03/03/2010
  • Est. Priority Date: 07/09/2004
  • Status: Active Grant
First Claim
Patent Images

1. integrated circuit comprises:

  • A) two feeder ears are configured to described integrated circuit power supply, and described feeder ear comprises positive feeder ear and earth terminal, and wherein, the voltage (VSS) of voltage of described positive feeder ear (VDD) and described earth terminal defines the scope of logic level jointly;

    B) logical block, described logical block are one that is selected from gate and the memory cell, and described logical block comprises sleep transistor, and one of described sleep transistor and described feeder ear are in series;

    C) voltage generator is configured to optionally to produce the voltage beyond the scope of described logic level;

    D) circuit is configured to during battery saving mode, and the voltage beyond the scope of described logic level is offered described sleep transistor;

    AndE) voltage regulator is configured to during battery saving mode, controls described voltage generator fully to reduce the leakage current by described sleep transistor, and described voltage regulator comprises emulated sleep.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×