For the filler cells of design optimization in place-and-route system

For the filler cells of design optimization in place-and-route system

  • CN 101,681,878 B
  • Filed: 07/30/2008
  • Issued: 01/13/2016
  • Est. Priority Date: 10/26/2007
  • Status: Active Grant
First Claim
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1. the method for layout integrated circuit (IC) design, for using together with database, described database limits multiple filler cells, described filler cells is pre-qualified, for adjusting the performance parameter of proximate circuitry layout units, layout is used for using according in the integrated circuit (IC)-components of design in manufacture, comprises step:

  • First layout of integrated circuit (IC) design is provided, described first layout limits multiple mask, described mask limits the physical features of multiple integrated circuit (IC)-components when applying in the fabrication process, described feature is limited to multiple circuit layout cells with gap therebetween, and these features are limited to the circuit structure of the integrated circuit (IC)-components of specifying in integrated circuit (IC) design together;

    AndCorresponding filler cells is inserted at least spacer concentrate each in fixed gap, corresponding filler cells selects from described database to the impact of the expectation in the performance parameter of at least one circuit layout cells of fixed gap according to adjacent to describedWherein said filler cells comprises the structure that can affect adjacent circuit layout units,The impact of wherein said expectation will improve performance parameter maybe will reduce the sensitiveness of performance parameter to the layout neighborhood of circuit layout cells, andWherein said performance parameter comprises the member in the group of transistor electron mobility, Ion, switch speed, signal path delay, leakage and power.

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