For the method manufacturing capacitive stack and electronic interconnection platform

For the method manufacturing capacitive stack and electronic interconnection platform

  • CN 101,682,989 B
  • Filed: 03/10/2008
  • Issued: 10/26/2016
  • Est. Priority Date: 03/10/2007
  • Status: Active Grant
First Claim
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1. , for the method manufacturing the capacitive stack with high capacitance density, described method includes:

  • Formed containing first dielectric layer being clipped between first conductive layer and second conductive layerThe planar core capacitive substrate of substantially rigid, the core capacitive substrate of wherein said substantially rigid provides to be usedIn coupling additional conductive foil and the rigidity of structure of dielectric layer;

    Described first conductive layer is formed the pattern in one or more gap;

    Before second dielectric layer is coupled to described first conductive layer, fill institute with epoxy resinState the one or more gap on first conductive layer;

    Described second dielectric layer is coated on first of the thickness having between 0.12 to 1 milConductive foil, described second dielectric layer includes being loaded with the nano powder being selected to realize expectation dielectric constantUncured or the dielectric material of semi-solid preparation at end, described second dielectric layer provides and 5 arrives per square inchCapacitance density between 60 nanofarads, and thickness is between 0.8 to 1 mil;

    The exposed surface of described second dielectric layer is coupled to described first conductive layer;

    Solidify the described dielectric material of described second dielectric layer;

    3rd dielectric layer is coated on second conductive foil, described 3rd dielectric layer include being loaded with throughSelect to realize expecting the dielectric material of the uncured or semi-solid preparation of the nanometer powder of dielectric constant;

    The exposed surface of described 3rd dielectric layer is coupled to described second conductive layer;

    Solidify the described dielectric material of described 3rd dielectric layer;

    Sequentially by described second dielectric layer and described 3rd dielectric layer and any follow-up JieElectric layer is added on the core capacitive substrate of described substantially rigid;

    When adding each dielectric layer, testThe integrity of the dielectric layer of this interpolation;

    AndOnce in the dielectric layer tested, it is found to have defect, scraps described capacitive stack immediately.

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