Dynamic processor power management device and method thereof

Dynamic processor power management device and method thereof

  • CN 101,755,250 A
  • Filed: 05/16/2008
  • Published: 06/23/2010
  • Est. Priority Date: 05/18/2007
  • Status: Active Application
First Claim
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1. method comprises:

  • Carry out first software in the first processor core between the first phase, this first processor core is in first electric source modes (303) between this first phase;

    Judge that in response to this first software between this first phase this first processor core is operable in the second source pattern, provide first to suspend indication (304);

    In response to receiving this first time-out indication, the first hardware module bus transaction that assessment is associated with bus in the second phase comprises this second phase (306) between this first phase;

    AndIn response to judging that this monitored bus transaction satisfies first and sounds out (307), provide first low supply voltage to this first processor core between the third phase, to allow this first processor core be in reserved state (308) between this third phase.

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