Method and system for facilitating floorplanning for 3D IC

Method and system for facilitating floorplanning for 3D IC

  • CN 101,821,745 A
  • Filed: 07/17/2009
  • Published: 09/01/2010
  • Est. Priority Date: 07/30/2008
  • Status: Active Application
First Claim
Patent Images

1. computer-executed method that is used to help three dimensional integrated circuits (3D IC) layout, described method comprises:

  • Receive a plurality of circuit blocks;

    Receive the parameter set of 3D structure, wherein said parameter comprises one or more parameter in the following parameter;

    Die area;

    Maximum total line length;

    The maximum number of the straight-through silicon path (TSV) on equivalent layer;

    AndThe aspect ratio of the equivalent layer in described 3D structure;

    AndBy optimizing the layout that cost function calculates the described circuit block of crossing over the layer in the described 3D structure, wherein at given layout, described cost function is based on the used total area of described circuit block, line length and TSV, the aspect ratio in the zone that the described circuit block in each layer occupies and the maximum temperature that is produced by described circuit block.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×