The System and method for of performance modeling of integrated circuit
The System and method for of performance modeling of integrated circuit
 CN 101,826,124 B
 Filed: 03/05/2010
 Issued: 06/29/2016
 Est. Priority Date: 03/06/2009
 Status: Active Grant
First Claim
Patent Images
1. method integrated circuit being performed TimeSeries analysis, said integrated circuit has a timing path, and said method includes:
 Calculate the quantity with sequential path element of the noncoin abovementioned timing path；
According only to the abovementioned noncoquantity with sequential path element, a sequential derating factor is specified to abovementioned timing path；
Use abovementioned specified sequential derating factor to calculate a TimeSeries analysis of said integrated circuit；
AndStore abovementioned computed TimeSeries analysis.
Chinese PRB Reexamination
Abstract
The present invention provides the System and method for of a kind of performance modeling of integrated circuit.The method that integrated circuit is performed TimeSeries analysis, wherein this integrated circuit has a timing path.The method includes the quantity calculating the noncoin timing path with sequential path element, one sequential derating factor is specified to timing path with the quantity of sequential path element according to nonco, use specified sequential derating factor to calculate a TimeSeries analysis of integrated circuit, and store computed TimeSeries analysis.
15 Claims

1. method integrated circuit being performed TimeSeries analysis, said integrated circuit has a timing path, and said method includes:

Calculate the quantity with sequential path element of the noncoin abovementioned timing path； According only to the abovementioned noncoquantity with sequential path element, a sequential derating factor is specified to abovementioned timing path； Use abovementioned specified sequential derating factor to calculate a TimeSeries analysis of said integrated circuit；
AndStore abovementioned computed TimeSeries analysis.


2. the method that integrated circuit is performed TimeSeries analysis as claimed in claim 1, is additionally included in the abovementioned noncoof calculating and performs with before the quantity of sequential path element:

Receive an IC design；
AndReceive one group of sequential derating factor.


3. the method that integrated circuit is performed TimeSeries analysis as claimed in claim 1, wherein said integrated circuit has multiple timing path, and the abovementioned noncoof abovementioned calculating also includes the noncocalculating each in the abovementioned timing path quantity with sequential path element with the step of the quantity of sequential path element.

4. the method that integrated circuit is performed TimeSeries analysis as claimed in claim 3, wherein the abovementioned step by abovementioned sequential derating factor appointment to abovementioned timing path also includes the quantity with sequential path element of the abovementioned noncoaccording to each in abovementioned timing path, and a sequential derating factor is specified each to abovementioned timing path.

5. the method that integrated circuit is performed TimeSeries analysis as claimed in claim 1, wherein the step of the abovementioned TimeSeries analysis of abovementioned calculating said integrated circuit also includes performing the TimeSeries analysis that a stagewise chip makes a variation.

6. appraising and deciding an integrated circuit method in order to manufacture, said integrated circuit has at least one timing path, and said method includes:

Receive an IC design； Calculate a Potency data of said integrated circuit by performing the TimeSeries analysis of each in the abovementioned timing path of said integrated circuit, and drop volume according only to the noncoin abovementioned timing path with each in abovementioned timing path to said integrated circuit of the quantity of sequential path element；
AndIn time judging that abovementioned Potency data meets multiple performance requirements, receive said integrated circuit design.


7. appraise and decide the integrated circuit method in order to manufacture as claimed in claim 6, also it is included in and judges when abovementioned Potency data does not meet abovementioned performance requirements, adjustment said integrated circuit designs, and wherein the step of abovementioned reception said integrated circuit design includes receiving a parasitic information of said integrated circuit, a delay information, a netlist, a time sequence information and a restricted information.

8. appraising and deciding the integrated circuit method in order to manufacture as claimed in claim 6, wherein the step of the abovementioned Potency data of abovementioned calculating said integrated circuit also includes:

Calculate the abovementioned noncoquantity with sequential path element of each in abovementioned timing path； According to the calculated abovementioned noncoquantity with sequential path element, a sequential derating factor is specified each to abovementioned timing path；
AndUse abovementioned specified sequential derating factor to calculate the TimeSeries analysis of said integrated circuit design.


9. appraise and decide the integrated circuit method in order to manufacture as claimed in claim 8, before being additionally included in the calculating abovementioned noncoquantity with sequential path element, receive one group of sequential derating factor.

10. appraising and deciding the integrated circuit method in order to manufacture as claimed in claim 9, wherein the step of abovementioned group of sequential derating factor of abovementioned reception includes fetching abovementioned group of sequential derating factor from a storage device.

11. appraise and decide the integrated circuit method in order to manufacture as claimed in claim 9, wherein the step of abovementioned group of sequential derating factor of abovementioned reception includes:

Perform a statistical simulation of a circuit design, in order to produce an analog result；
AndAccording to abovementioned analog result, setting up abovementioned group of sequential derating factor, wherein abovementioned statistical simulation uses Monte Carlo simulation technology.


12. appraise and decide the integrated circuit method in order to manufacture as claimed in claim 11, it is additionally included in before setting up abovementioned group of sequential derating factor, tunes abovementioned analog result.

13. appraise and decide the integrated circuit method in order to manufacture as claimed in claim 12, wherein the step of the abovementioned analog result of abovementioned tuning includes multiple standard deviations of the computed meansigma methods of appointment, in order to produce a confidence interval.

14. appraise and decide the integrated circuit method in order to manufacture as claimed in claim 12, wherein the step of the abovementioned analog result of abovementioned tuning includes specifying a margin, and wherein the pessimistic value of abovementioned margin presets the pessimistic value of margin higher than in order to set up abovementioned group of sequential derating factor.

15. perform a system for the TimeSeries analysis of IC design, said system includes:

One sequential path selection unit, in order to select the multiple timing paths in said integrated circuit design； One stagewise derating factor selects unit, it is coupled to abovementioned timing path and selects unit, abovementioned stagewise derating factor selects unit according only to the quantity with sequential path element of the noncoin abovementioned timing path, is specified by a sequential derating factor to abovementioned timing path and selects each of abovementioned timing path selected by unit；
AndThe analysis engine of one stagewise chip variation, it is coupled to abovementioned stagewise derating factor and selects unit, the abovementioned sequential derating factor of the analysis engine of the abovementioned stagewise chip variation each by being designated in the abovementioned timing path of said integrated circuit design, calculates a time sequence information of said integrated circuit design.

Specification(s)