Method and apparatus for operating nonvolatile memory with floating voltage at one of the source and drain regions

Method and apparatus for operating nonvolatile memory with floating voltage at one of the source and drain regions

  • CN 101,866,693 A
  • Filed: 11/08/2007
  • Published: 10/20/2010
  • Est. Priority Date: 11/17/2006
  • Status: Active Application
First Claim
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1. method of operating the semiconductor memory cell array comprises:

  • A plurality of memory cell arrangements become at least one row, and each described storage unit has a grid, one first diffusion zone, one second diffusion zone, one first charge-trapping position, one second charge-trapping position;

    Many word lines list one with a plurality of grids and are connected;

    Many first bit lines are connected with a plurality of first diffusion zones;

    Many second bit lines are connected with a plurality of second diffusion zones;

    Wherein programmed in described first charge-trapping position and the described second charge-trapping position by following steps;

    Bias voltage one first voltage is to described many word lines;

    Bias voltage one second voltage is to described many first bit lines;

    AndWith described many second bit line suspension joints.

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