SOIMOS (Silicon on Insulator Metal Oxide Semiconductor) device with BTS (Bodied Tied to Source) structure and manufacture method thereof

SOIMOS (Silicon on Insulator Metal Oxide Semiconductor) device with BTS (Bodied Tied to Source) structure and manufacture method thereof

  • CN 101,916,776 B
  • Filed: 07/13/2010
  • Issued: 07/22/2015
  • Est. Priority Date: 07/13/2010
  • Status: Active Grant
First Claim
Patent Images

1. there is a manufacture method for the SOIMOS device of BTS structure, it is characterized in that, comprise the following steps:

  • Step one, on the Si material with insulating buried layer, make fleet plough groove isolation structure, isolate part Si material, and make grid region on this part Si material;

    Step 2, carry out source region light dope and drain region light dope, form lightly doped n-type source region and lightly doped n-type drain region, described source region light dope and drain region light dope implantation dosage reach 1e15/cm 2magnitude, the concentration in described lightly doped n-type source region and lightly doped n-type drain region reaches 1e19/cm 3magnitude;

    Step 3, around grid region, make side wall isolation structure, the part surface in lightly doped n-type source region and lightly doped n-type drain region covers by described side wall isolation structure, then source region and drain region ion implantation is carried out, form N-type Si material source region and N-type drain region, between described N-type Si material source region and N-type drain region, form tagma;

    Described N-type Si material source region is made up of the shallow n-type district below side wall isolation structure and heavily doped N-type region territory;

    Step 4, method by ion implantation, ion is not injected downwards by the surface that side wall isolation structure covers from N-type Si material source region, heavily doped P-type district is formed at the middle part in its heavily doped N-type region territory, described heavily doped N-type region territory is divided into Liang Ge heavily doped N-type district by this heavily doped P-type district, wherein, the position together in the middle part of described heavily doped N-type region territory is adopted to be provided with opening, and the mask plate of this opening and side wall isolation structure justified margin, vertically carry out heavy doping P ion implantation via this mask plate, thus form heavily doped P-type district;

    Step 5, form layer of metal on the surface in heavily doped P-type district and Liang Ge heavily doped N-type district, then by heat treatment, this metal and the Si material under it are reacted and generate silicide, this silicide is contacted with described heavily doped P-type district and Liang Ge heavily doped N-type district, the silicide generated and heavily doped P-type district, Liang Ge heavily doped N-type district and shallow n-type district form N-type source region, described heat treated temperature is 700-900 DEG C, time is 50-70 second, finally completes MOS device structure.

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