The method for designing of digital baseband chip, GSM channel coding/decoding and implementation method

The method for designing of digital baseband chip, GSM channel coding/decoding and implementation method

  • CN 101,932,127 B
  • Filed: 06/23/2009
  • Issued: 05/18/2016
  • Est. Priority Date: 06/23/2009
  • Status: Active Grant
First Claim
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1. a method for designing that realizes GSM channel coding/decoding in digital baseband chip, is characterized in that, described methodComprise the following steps:

  • (1) calculate input data information and the logic of exporting data message according to the protocol specification of GSM channel coding/decodingAssociated correspondence relationship information;

    Comprise the following steps;

    (11), according to the protocol specification of GSM channel coding/decoding, programme and calculate input data ratio by high-level [computerThe corresponding line relation of logic association between spy and output data bit;

    (12) according to described logic association corresponding relation, the input data bit sequence number corresponding with output data bit writeIn storage medium,(2) generate corresponding chip logic design code according to obtained logic association correspondence relationship information;

    (3) described chip logic design code is converted to net table information, and burning enters in digital baseband chip;

    DescribedThe protocol specification of GSM channel coding/decoding is GSM voice channel coding/decoding protocol specification;

    Described GSM voice channel is compiledCode/decoding protocol specification is GSM voice channel TCH/EFS coding/decoding protocol specification,Logic association corresponding relation between described input data bit and output data bit specifically comprises;

    (1) the logic association corresponding relation of input data s bit and required each bit of calculating cyclic redundancy check code CRC8;

    (2) the logic association corresponding relation of input data s bit and required each bit of calculating cyclic redundancy check code CRC3;

    (3) input data s bit and CRC CRC3 and the corresponding pass of logic association of exporting data first order u bitSystem;

    (4) input data s bit and CRC CRC8 and the corresponding pass of logic association of exporting data second level d bitSystem.

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