Circuits and methods for sleep state leakage current reduction

Circuits and methods for sleep state leakage current reduction

  • CN 101,978,602 A
  • Filed: 02/03/2009
  • Published: 02/16/2011
  • Est. Priority Date: 02/15/2008
  • Status: Active Application
First Claim
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1. circuit, it comprises:

  • Hardware cell, it is selected from latch, trigger, comparator, multiplexer or the adder at least one, and described hardware cell comprises;

    First node;

    AndCombinational logic is enabled in sleep, and it is coupled to described first node, wherein keeps the value of described first node during sleep state.

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