Chip package and fabrication method thereof

Chip package and fabrication method thereof

  • CN 101,996,953 A
  • Filed: 08/10/2010
  • Published: 03/30/2011
  • Est. Priority Date: 08/19/2009
  • Status: Active Application
First Claim
Patent Images

1. chip packing-body comprises:

  • Semiconductor substrate has opposite first surface and second surface, and at least one connection pad district and at least one element region;

    A plurality of conductive pad structures are positioned at the first surface of this semiconductor substrate, and are positioned in this connection pad district of this semiconductor substrate;

    The heavily doped region of a plurality of mutual isolation is located at those conductive pad structure belows, and is electrically connected with those conductive pad structures;

    AndA plurality of conductive projections are located at those heavily doped region belows, and are electrically connected with those conductive pad structures formation via those heavily doped regions.

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