Method of reducing memory effects in semiconductor epitaxy

Method of reducing memory effects in semiconductor epitaxy

  • CN 102,057,078 B
  • Filed: 05/29/2009
  • Issued: 04/01/2015
  • Est. Priority Date: 06/04/2008
  • Status: Active Grant
First Claim
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1. be reduced in a method for the memory effect in the epitaxial process of semiconductor material, the method comprises:

  • Reaction chamber is provided;

    Semiconductor base is provided;

    One or more precursor gases are provided;

    On described semiconductor base, the extension CVD growth of the semiconductor material adulterated is carried out in described reaction chamber, to form the first layer on described semiconductor base, be wherein included in the assistant depositing thing in reaction chamber wall in the low flow region of the gas entrapment of partial reaction in reaction chamber;

    Wash away described reaction chamber with the gaseous mixture comprising hydrogen and halogen-containing gas, with the gas of the partial reaction of catching described in removing, and do not remove the described assistant depositing thing from reaction zone significantly;

    WithAfter washing away, in described reaction chamber, on described semiconductor base, carry out the extension CVD growth of the semiconductor material adulterated, to form the second layer on described semiconductor base;

    Wherein said semiconductor material is silicon carbide and described semiconductor base is SiC, andWherein at the temperature of 1300 DEG C-1600 DEG C, wash away described reaction chamber.

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