Power semiconductor device and manufacturing method therefor

Power semiconductor device and manufacturing method therefor

  • CN 102,074,536 B
  • Filed: 10/14/2010
  • Issued: 02/04/2015
  • Est. Priority Date: 10/15/2009
  • Status: Active Grant
First Claim
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1. a power semiconductor arrangement, is characterized in that, comprising:

  • Substrate;

    Element circuit pattern is formed on described substrate, covered the structure of Cu by non-electrolytic Ni-P coating;

    AndPower semiconductor, its by scolding tin and described element circuit pattern affixed,Described scolding tin is the alloy of Sn and Sb and Cu, and the percentage by weight of Cu is the arbitrary value of less than more than 0.5% 1%,The percentage by weight of the Sn of described alloy is the arbitrary value of less than more than 91% 93%, and the percentage by weight of Sb is the arbitrary value of less than more than 6.5% 8%.

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