Debug method of FPGA and equipment thereof

Debug method of FPGA and equipment thereof

  • CN 102,103,186 A
  • Filed: 12/18/2009
  • Published: 06/22/2011
  • Est. Priority Date: 12/18/2009
  • Status: Active Application
First Claim
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1. on-site programmable gate array FPGA adjustment method comprises:

  • Before CPU starts, the FPGA configuration data is stored in the flash memory by complex programmable logic device (CPLD);

    Described CPLD sets up the effective passage between FPGA and the described flash memory, is used for debugging so that described FPGA can obtain described configuration data by described effective passage.

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