A sub-stage for a charge pump

A sub-stage for a charge pump

  • CN 102,104,329 A
  • Filed: 12/15/2010
  • Published: 06/22/2011
  • Est. Priority Date: 12/18/2009
  • Status: Active Application
First Claim
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1. secondary units (212) that is used to have the charge pump (200) of first and second operational phases, described secondary units (212) comprising:

  • Dc input pin (222);

    Dc output pin (220);

    The one rf input pin (202), configuration is used to receive first differential signal;

    The 2nd rf input pin (204), configuration is used to receive second differential signal;

    The first transistor (224) has first, second and the 3rd terminal, wherein provides current channel between first and second terminals of this transistor (224);

    AndTransistor seconds (226) has first, second and the 3rd terminal, wherein provides current channel between first and second terminals of this transistor (226);

    The first terminal of wherein said the first transistor (224) links to each other with described dc input pin (222), second terminal of described the first transistor (224) links to each other with the first terminal of described transistor seconds (226), and second terminal of described transistor seconds (226) links to each other with described dc output pin (220);

    A wherein said rf input pin (202) links to each other with second terminal of described the first transistor (224) and the first terminal of transistor seconds (226), make during described first operational phase, the signaling that the current channel conduction of described the first transistor (224) is located to receive at a described rf input pin (202), and during described second operational phase, the signaling that the current channel conduction of described transistor seconds (226) is located to receive at a described rf input pin (202)Described secondary units (212) also comprises first bias voltage source (232) and second bias voltage source (234);

    The 3rd terminal arrangement of wherein said the first transistor (224) is used for receiving second differential signal and receiving first offset voltage signal from described first bias voltage source (232) from described the 2nd rf input pin (204);

    AndThe 3rd terminal arrangement of described transistor seconds (226) is used for receiving second differential signal and receiving second offset voltage signal from described second bias voltage source (234) from described the 2nd rf input pin (204).

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